doc/README.440-DDR-performance · 7168da163880fc60c4e8d00f3d61eb6f009ffe56 · Florian Mayer / u-boot

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18 years ago

PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance · a2c95a72

Stefan Roese authored 18 years ago

AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006

a2c95a72

History

PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance

Stefan Roese authored 18 years ago

AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006