doc/README.mpc85xx-spin-table · 7168da163880fc60c4e8d00f3d61eb6f009ffe56 · Florian Mayer / u-boot

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12 years ago

powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 · ffd06e02

York Sun authored 12 years ago


Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

ffd06e02

History

powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

York Sun authored 12 years ago


Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>