diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 0c8e6cb701e909f7a155bd9a2966aa69b3f6d333..f1c352cb86e32fbeb2a6b5edece824a57e4ee454 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -35,9 +35,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
-
int board_early_init_f (void)
{
unsigned long mfr;
@@ -409,9 +406,9 @@ void pcie_setup_hoses(int busno)
continue;
#ifdef PCIE_ENDPOINT
- if (ppc440spe_init_pcie_endport(i)) {
+ if (ppc4xx_init_pcie_endport(i)) {
#else
- if (ppc440spe_init_pcie_rootport(i)) {
+ if (ppc4xx_init_pcie_rootport(i)) {
#endif
printf("PCIE%d: initialization failed\n", i);
continue;
@@ -433,13 +430,13 @@ void pcie_setup_hoses(int busno)
pci_register_hose(hose);
#ifdef PCIE_ENDPOINT
- ppc440spe_setup_pcie_endpoint(hose, i);
+ ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
#else
- ppc440spe_setup_pcie_rootpoint(hose, i);
+ ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 17c3ba0f17d02f739269f21f8b81a48b0aa1dae9..c46721c9229f99cc196bace2700dc2202258e310 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -47,9 +47,6 @@ char *remove_l_w_space(char *in_str );
char *remove_t_w_space(char *in_str );
int get_console_port(void);
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
-
#define DEBUG_ENV
#ifdef DEBUG_ENV
#define DEBUGF(fmt,args...) printf(fmt ,##args)
@@ -865,10 +862,10 @@ void pcie_setup_hoses(int busno)
#ifdef PCIE_ENDPOINT
yucca_setup_pcie_fpga_endpoint(i);
- if (ppc440spe_init_pcie_endport(i)) {
+ if (ppc4xx_init_pcie_endport(i)) {
#else
yucca_setup_pcie_fpga_rootpoint(i);
- if (ppc440spe_init_pcie_rootport(i)) {
+ if (ppc4xx_init_pcie_rootport(i)) {
#endif
printf("PCIE%d: initialization failed\n", i);
continue;
@@ -890,13 +887,13 @@ void pcie_setup_hoses(int busno)
pci_register_hose(hose);
#ifdef PCIE_ENDPOINT
- ppc440spe_setup_pcie_endpoint(hose, i);
+ ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
#else
- ppc440spe_setup_pcie_rootpoint(hose, i);
+ ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 8906adc51e24a7cd8a610d2e3e311b58d00c7454..c7b21417861f3d8d7c4cff36cfa5000691ea6508 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -222,7 +222,7 @@ int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset
return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
}
-static void ppc440spe_setup_utl(u32 port) {
+static void ppc4xx_setup_utl(u32 port) {
volatile void *utl_base = NULL;
@@ -333,7 +333,7 @@ static int check_error(void)
/*
* Initialize PCI Express core
*/
-int ppc440spe_init_pcie(void)
+int ppc4xx_init_pcie(void)
{
int time_out = 20;
@@ -401,7 +401,7 @@ int ppc440spe_init_pcie(void)
* which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
* data at 0x9000 0000(SRAM).Data should match.
*/
-int ppc440spe_init_pcie_rootport(int port)
+int ppc4xx_init_pcie_rootport(int port)
{
static int core_init;
volatile u32 val = 0;
@@ -409,7 +409,7 @@ int ppc440spe_init_pcie_rootport(int port)
if (!core_init) {
++core_init;
- if (ppc440spe_init_pcie())
+ if (ppc4xx_init_pcie())
return -1;
}
@@ -520,7 +520,7 @@ int ppc440spe_init_pcie_rootport(int port)
* We use default settings for revB chip.
*/
if (!ppc440spe_revB())
- ppc440spe_setup_utl(port);
+ ppc4xx_setup_utl(port);
/*
* We map PCI Express configuration access into the 512MB regions
@@ -620,7 +620,7 @@ int ppc440spe_init_pcie_rootport(int port)
return 0;
}
-int ppc440spe_init_pcie_endport(int port)
+int ppc4xx_init_pcie_endport(int port)
{
static int core_init;
volatile u32 val = 0;
@@ -628,7 +628,7 @@ int ppc440spe_init_pcie_endport(int port)
if (!core_init) {
++core_init;
- if (ppc440spe_init_pcie())
+ if (ppc4xx_init_pcie())
return -1;
}
@@ -734,7 +734,7 @@ int ppc440spe_init_pcie_endport(int port)
* We use default settings for revB chip.
*/
if (!ppc440spe_revB())
- ppc440spe_setup_utl(port);
+ ppc4xx_setup_utl(port);
/*
* We map PCI Express configuration access into the 512MB regions
@@ -833,7 +833,7 @@ int ppc440spe_init_pcie_endport(int port)
return 0;
}
-void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
+void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
volatile void *rmbase = NULL;
@@ -951,7 +951,7 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
}
-int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
+int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
int attempts = 0;
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index 38745eb797cdafa230c93cedd32db04bd12fa21a..220c60cd761401fa3c4e64908bbd560304f0c95e 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -9,8 +9,8 @@
*/
#include <ppc4xx.h>
-#ifndef __440SPE_PCIE_H
-#define __440SPE_PCIE_H
+#ifndef __4XX_PCIE_H
+#define __4XX_PCIE_H
#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
@@ -164,11 +164,10 @@
#define GPL_DMER_MASK_DISA 0x02000000
-int ppc440spe_init_pcie(void);
-int ppc440spe_init_pcie_rootport(int port);
-void yucca_setup_pcie_fpga_rootpoint(int port);
-void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port);
-int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port);
-int yucca_pcie_card_present(int port);
+int ppc4xx_init_pcie(void);
+int ppc4xx_init_pcie_rootport(int port);
+void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
+int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);
-#endif /* __440SPE_PCIE_H */
+
+#endif /* __4XX_PCIE_H */