From 092da485c7e685745b6e6f9ab5540fb002046201 Mon Sep 17 00:00:00 2001
From: Prabhakar Kushwaha <prabhakar at freescale.com>
Date: Thu, 28 May 2015 14:54:11 +0530
Subject: [PATCH] armv8/ls2085a: Update SoC README for DDR layout

Update SoC README to provide details of
 - Memory regions
 - Memory used by MC and Debug server

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---
 arch/arm/cpu/armv8/fsl-lsch3/README | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index 37f07fbb76e..3c154793157 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -9,6 +9,31 @@ Freescale LayerScape with Chassis Generation 3
 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
 for example LS2085A.
 
+DDR Layout
+============
+Entire DDR region splits into two regions.
+ - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
+ - Region 2 is at 0x80_8000_0000 to the top of total memory,
+   for example 16GB, 0x83_ffff_ffff.
+
+All DDR memory is marked as cache-enabled.
+
+When MC and Debug server is enabled, they carve 512MB away from the high
+end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
+with MC and Debug server enabled. Linux only sees 15.5GB.
+
+The reserved 512MB layout looks like
+
+   +---------------+ <-- top/end of memory
+   |    256MB      |  debug server
+   +---------------+
+   |    256MB      |  MC
+   +---------------+
+   |     ...       |
+
+MC requires the memory to be aligned with 512MB, so even debug server is
+not enabled, 512MB is reserved, not 256MB.
+
 Flash Layout
 ============
 
-- 
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