diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8458f6bed85c9c7abf5d922b68a03ec419102758..8dbaea0f8d4cd96f0a922ff3af46b19d2b0a08fe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -79,18 +79,18 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-theadorable.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
- uniphier-ph1-ld11-ref.dtb \
- uniphier-ph1-ld20-ref.dtb \
- uniphier-ph1-ld4-ref.dtb \
- uniphier-ph1-ld6b-ref.dtb \
- uniphier-ph1-pro4-ace.dtb \
- uniphier-ph1-pro4-ref.dtb \
- uniphier-ph1-pro4-sanji.dtb \
- uniphier-ph1-pro5-4kbox.dtb \
- uniphier-ph1-sld3-ref.dtb \
- uniphier-ph1-sld8-ref.dtb \
- uniphier-proxstream2-gentil.dtb \
- uniphier-proxstream2-vodka.dtb
+ uniphier-ld11-ref.dtb \
+ uniphier-ld20-ref.dtb \
+ uniphier-ld4-ref.dtb \
+ uniphier-ld6b-ref.dtb \
+ uniphier-pro4-ace.dtb \
+ uniphier-pro4-ref.dtb \
+ uniphier-pro4-sanji.dtb \
+ uniphier-pro5-4kbox.dtb \
+ uniphier-pxs2-gentil.dtb \
+ uniphier-pxs2-vodka.dtb \
+ uniphier-sld3-ref.dtb \
+ uniphier-sld8-ref.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index e4410339eb64b2821700ea110692cc6f138c1b58..f87e3208309547131a26f250e9a413b15a0557ba 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -1,7 +1,8 @@
/*
* Device Tree Source commonly used by UniPhier ARM SoCs
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,6 +10,11 @@
/include/ "skeleton.dtsi"
/ {
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
refclk: ref {
#clock-cells = <0>;
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts
similarity index 78%
rename from arch/arm/dts/uniphier-ph1-ld11-ref.dts
rename to arch/arm/dts/uniphier-ld11-ref.dts
index ca310267380431e3b704ee8637c15a9614c6f5ab..ea1119897682378e3fa442c5638ce1ca01043c82 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ld11-ref.dts
@@ -1,5 +1,5 @@
/*
- * Device Tree Source for UniPhier PH1-LD11 Reference Board
+ * Device Tree Source for UniPhier LD11 Reference Board
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
@@ -8,12 +8,13 @@
*/
/dts-v1/;
-/include/ "uniphier-ph1-ld11.dtsi"
+/include/ "uniphier-ld11.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-LD11 Reference Board";
- compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
+ model = "UniPhier LD11 Reference Board";
+ compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
aliases {
serial0 = &serial0;
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
similarity index 93%
rename from arch/arm/dts/uniphier-ph1-ld11.dtsi
rename to arch/arm/dts/uniphier-ld11.dtsi
index 0bdbbddd9dde20aef63026172eb275d118ac6b27..a95cb6e97bd14bfec5be3a756251ac1decccf329 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -1,5 +1,5 @@
/*
- * Device Tree Source for UniPhier PH1-LD11 SoC
+ * Device Tree Source for UniPhier LD11 SoC
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
@@ -10,7 +10,7 @@
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
- compatible = "socionext,ph1-ld11";
+ compatible = "socionext,uniphier-ld11";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
@@ -230,7 +230,9 @@
interrupts = <0 243 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb1: usb@5a810100 {
@@ -240,7 +242,9 @@
interrupts = <0 244 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
usb2: usb@5a820100 {
@@ -250,7 +254,9 @@
interrupts = <0 245 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
};
mioctrl@5b3e0000 {
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts
similarity index 70%
rename from arch/arm/dts/uniphier-ph1-ld20-ref.dts
rename to arch/arm/dts/uniphier-ld20-ref.dts
index e4e8d7674900c0255dc11a5ca45d65981598d931..044e0007492c0b6206b2768d809103f6da381604 100644
--- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts
+++ b/arch/arm/dts/uniphier-ld20-ref.dts
@@ -1,19 +1,20 @@
/*
- * Device Tree Source for UniPhier PH1-LD20 Reference Board
+ * Device Tree Source for UniPhier LD20 Reference Board
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-ld20.dtsi"
+/include/ "uniphier-ld20.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-LD20 Reference Board";
- compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
+ model = "UniPhier LD20 Reference Board";
+ compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
aliases {
serial0 = &serial0;
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
similarity index 96%
rename from arch/arm/dts/uniphier-ph1-ld20.dtsi
rename to arch/arm/dts/uniphier-ld20.dtsi
index 7f97f8816a4ddf51a17508d8b5ca734043fcaeba..29a84aeccdd8500ae1e71917905409189626c271 100644
--- a/arch/arm/dts/uniphier-ph1-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier PH1-LD20 SoC
+ * Device Tree Source for UniPhier LD20 SoC
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,7 +10,7 @@
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
- compatible = "socionext,ph1-ld20";
+ compatible = "socionext,uniphier-ld20";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
@@ -271,6 +272,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>;
clocks = <&mio_clk 0>;
+ reset-names = "host";
+ resets = <&mio_rst 0>;
bus-width = <4>;
};
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts
similarity index 72%
rename from arch/arm/dts/uniphier-ph1-ld4-ref.dts
rename to arch/arm/dts/uniphier-ld4-ref.dts
index 36de7e3a0f9680c1cec5b6abc52e8df69727080f..0f4bd9bda227f813ab61490cc496a8ed1920f8ea 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ld4-ref.dts
@@ -1,19 +1,20 @@
/*
- * Device Tree Source for UniPhier PH1-LD4 Reference Board
+ * Device Tree Source for UniPhier LD4 Reference Board
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-ld4.dtsi"
+/include/ "uniphier-ld4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-LD4 Reference Board";
- compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";
+ model = "UniPhier LD4 Reference Board";
+ compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
similarity index 89%
rename from arch/arm/dts/uniphier-ph1-ld4.dtsi
rename to arch/arm/dts/uniphier-ld4.dtsi
index e4884b9516c361a219c3dbcc597996e61a1bd705..9f555df652d6411cced35d598a47f06078578272 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier PH1-LD4 SoC
+ * Device Tree Source for UniPhier LD4 SoC
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,7 +10,7 @@
/include/ "uniphier-common32.dtsi"
/ {
- compatible = "socionext,ph1-ld4";
+ compatible = "socionext,uniphier-ld4";
cpus {
#address-cells = <1>;
@@ -19,6 +20,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
};
@@ -223,6 +225,8 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
};
@@ -235,6 +239,8 @@
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
bus-width = <8>;
non-removable;
};
@@ -246,7 +252,9 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb1: usb@5a810100 {
@@ -256,7 +264,9 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
usb2: usb@5a820100 {
@@ -266,7 +276,9 @@
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
};
aidet@61830000 {
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts
similarity index 73%
rename from arch/arm/dts/uniphier-ph1-ld6b-ref.dts
rename to arch/arm/dts/uniphier-ld6b-ref.dts
index e29a6ea841f1d6ea6c6c964d96d339cec85fde3a..4da3c63f7367b038a45f084e79ceda9135a4e2ff 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ld6b-ref.dts
@@ -1,19 +1,20 @@
/*
- * Device Tree Source for UniPhier PH1-LD6b Reference Board
+ * Device Tree Source for UniPhier LD6b Reference Board
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
-/include/ "uniphier-ph1-ld6b.dtsi"
+/include/ "uniphier-ld6b.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-LD6b Reference Board";
- compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b";
+ model = "UniPhier LD6b Reference Board";
+ compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ld6b.dtsi b/arch/arm/dts/uniphier-ld6b.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..9870047f458e257e6ca783b0619abc2a035edfbe
--- /dev/null
+++ b/arch/arm/dts/uniphier-ld6b.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Device Tree Source for UniPhier LD6b SoC
+ *
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/*
+ * LD6b consists of two silicon dies: D-chip and A-chip.
+ * The D-chip (digital chip) is the same as the PXs2 die.
+ * Reuse the PXs2 device tree with some properties overridden.
+ */
+/include/ "uniphier-pxs2.dtsi"
+
+/ {
+ compatible = "socionext,uniphier-ld6b";
+};
+
+/* UART3 unavailable: the pads are not wired to the package balls */
+&serial3 {
+ status = "disabled";
+};
+
+/*
+ * LD6b and PXs2 have completely different packages,
+ * which makes the pinctrl driver unshareable.
+ */
+&pinctrl {
+ compatible = "socionext,uniphier-ld6b-pinctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/dts/uniphier-ph1-ld6b.dtsi
deleted file mode 100644
index e8110eefcec41306d541d4db7302113fe1c1e4d9..0000000000000000000000000000000000000000
--- a/arch/arm/dts/uniphier-ph1-ld6b.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Device Tree Source for UniPhier PH1-LD6b SoC
- *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
-
-/*
- * PH1-LD6b consists of two silicon dies: D-chip and A-chip.
- * The D-chip (digital chip) is the same as the ProXstream2 die.
- * Reuse the ProXstream2 device tree with some properties overridden.
- */
-/include/ "uniphier-proxstream2.dtsi"
-
-/ {
- compatible = "socionext,ph1-ld6b";
-};
-
-/* UART3 unavailable: the pads are not wired to the package balls */
-&serial3 {
- status = "disabled";
-};
-
-/*
- * PH1-LD6b and ProXstream2 have completely different packages,
- * which makes the pinctrl driver unshareable.
- */
-&pinctrl {
- compatible = "socionext,uniphier-ld6b-pinctrl";
-};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
similarity index 72%
rename from arch/arm/dts/uniphier-ph1-pro4-ace.dts
rename to arch/arm/dts/uniphier-pro4-ace.dts
index d8740cc9d33f3a2d8f536719a0f3654ad187a52e..f70bc82e25735ff4130022158e0725728738cbba 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -1,17 +1,18 @@
/*
- * Device Tree Source for UniPhier PH1-Pro4 Ace Board
+ * Device Tree Source for UniPhier Pro4 Ace Board
*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
+/include/ "uniphier-pro4.dtsi"
/ {
- model = "UniPhier PH1-Pro4 Ace Board";
- compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
+ model = "UniPhier Pro4 Ace Board";
+ compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
memory {
device_type = "memory";
@@ -50,8 +51,8 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "24c64", "i2c-eeprom";
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
reg = <0x54>;
u-boot,i2c-offset-len = <2>;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts
similarity index 74%
rename from arch/arm/dts/uniphier-ph1-pro4-ref.dts
rename to arch/arm/dts/uniphier-pro4-ref.dts
index 4a2de08e0668b357dd42f03060a59f73c0cabcd7..2d49b3e831ad6c52c1aa9904dd7d80ef1e21278b 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-pro4-ref.dts
@@ -1,19 +1,20 @@
/*
- * Device Tree Source for UniPhier PH1-Pro4 Reference Board
+ * Device Tree Source for UniPhier Pro4 Reference Board
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
+/include/ "uniphier-pro4.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-Pro4 Reference Board";
- compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4";
+ model = "UniPhier Pro4 Reference Board";
+ compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
similarity index 73%
rename from arch/arm/dts/uniphier-ph1-pro4-sanji.dts
rename to arch/arm/dts/uniphier-pro4-sanji.dts
index 3f178d239add6587d5443d4a1c406b97714a1e1a..d43f725b39a05654c26fa814e19ff8c0bb182d79 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -1,17 +1,18 @@
/*
- * Device Tree Source for UniPhier PH1-Pro4 Sanji Board
+ * Device Tree Source for UniPhier Pro4 Sanji Board
*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-pro4.dtsi"
+/include/ "uniphier-pro4.dtsi"
/ {
- model = "UniPhier PH1-Pro4 Sanji Board";
- compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
+ model = "UniPhier Pro4 Sanji Board";
+ compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
memory {
device_type = "memory";
@@ -45,8 +46,8 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "24c64", "i2c-eeprom";
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
reg = <0x54>;
u-boot,i2c-offset-len = <2>;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
similarity index 93%
rename from arch/arm/dts/uniphier-ph1-pro4.dtsi
rename to arch/arm/dts/uniphier-pro4.dtsi
index 192ce841e1379809c9efae5b456f066bbd1a507a..aa80ea4801f26ba20fdd96399038bb3fbf85ded4 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier PH1-Pro4 SoC
+ * Device Tree Source for UniPhier Pro4 SoC
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,17 +10,17 @@
/include/ "uniphier-common32.dtsi"
/ {
- compatible = "socionext,ph1-pro4";
+ compatible = "socionext,uniphier-pro4";
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -27,6 +28,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
};
@@ -352,6 +354,8 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
};
@@ -364,6 +368,8 @@
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
bus-width = <8>;
non-removable;
};
@@ -377,6 +383,7 @@
pinctrl-0 = <&pinctrl_sd1>;
pinctrl-1 = <&pinctrl_sd1_1v8>;
clocks = <&mio_clk 2>;
+ resets = <&mio_rst 2>, <&mio_rst 5>;
bus-width = <4>;
};
@@ -387,7 +394,9 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb3: usb@5a810100 {
@@ -397,7 +406,9 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
aidet@5fc20000 {
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-pro5-4kbox.dts
similarity index 64%
rename from arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
rename to arch/arm/dts/uniphier-pro5-4kbox.dts
index 682b7958fa2573dacc1a19321c4456b01c053da6..ffc21a7c500c5ab817b0f776c4554fd084d86069 100644
--- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
+++ b/arch/arm/dts/uniphier-pro5-4kbox.dts
@@ -1,17 +1,18 @@
/*
- * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
+ * Device Tree Source for UniPhier Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
-/include/ "uniphier-ph1-pro5.dtsi"
+/include/ "uniphier-pro5.dtsi"
/ {
- model = "UniPhier PH1-Pro5 4KBOX Board";
- compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
+ model = "UniPhier Pro5 4KBOX Board";
+ compatible = "socionext,uniphier-pro5-4kbox", "socionext,uniphier-pro5";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
similarity index 96%
rename from arch/arm/dts/uniphier-ph1-pro5.dtsi
rename to arch/arm/dts/uniphier-pro5.dtsi
index 22a70b1a601ce04578ea5cf4123cd141d34ad6e8..97edc89a9cc89916ed1950312f91fda28d4ae134 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier PH1-Pro5 SoC
+ * Device Tree Source for UniPhier Pro5 SoC
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,17 +10,17 @@
/include/ "uniphier-common32.dtsi"
/ {
- compatible = "socionext,ph1-pro5";
+ compatible = "socionext,uniphier-pro5";
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -27,6 +28,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
};
@@ -362,6 +364,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
+ reset-names = "host", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 6>;
bus-width = <8>;
non-removable;
};
@@ -375,6 +379,8 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
+ reset-names = "host";
+ resets = <&mio_rst 0>;
bus-width = <4>;
};
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
similarity index 69%
rename from arch/arm/dts/uniphier-proxstream2-gentil.dts
rename to arch/arm/dts/uniphier-pxs2-gentil.dts
index 7233dc67ab3ffcb80ea750240c89b47c3dfb5e56..a98e758f031902c012e9b8f41970179a8fb38551 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -1,17 +1,19 @@
/*
- * Device Tree Source for UniPhier ProXstream2 Gentil Board
+ * Device Tree Source for UniPhier PXs2 Gentil Board
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
-/include/ "uniphier-proxstream2.dtsi"
+/include/ "uniphier-pxs2.dtsi"
/ {
- model = "UniPhier ProXstream2 Gentil Board";
- compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
+ model = "UniPhier PXs2 Gentil Board";
+ compatible = "socionext,uniphier-pxs2-gentil",
+ "socionext,uniphier-pxs2";
memory {
device_type = "memory";
@@ -41,8 +43,8 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "24c64", "i2c-eeprom";
+ eeprom@54 {
+ compatible = "st,24c64", "i2c-eeprom";
reg = <0x54>;
u-boot,i2c-offset-len = <2>;
};
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts
similarity index 69%
rename from arch/arm/dts/uniphier-proxstream2-vodka.dts
rename to arch/arm/dts/uniphier-pxs2-vodka.dts
index 30ea27034c696aa16313447ab2314dff5296b5fe..78a52a8f18f16f5baf810aa8017a207347b630e1 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-pxs2-vodka.dts
@@ -1,17 +1,18 @@
/*
- * Device Tree Source for UniPhier ProXstream2 Vodka Board
+ * Device Tree Source for UniPhier PXs2 Vodka Board
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
-/include/ "uniphier-proxstream2.dtsi"
+/include/ "uniphier-pxs2.dtsi"
/ {
- model = "UniPhier ProXstream2 Vodka Board";
- compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
+ model = "UniPhier PXs2 Vodka Board";
+ compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
similarity index 95%
rename from arch/arm/dts/uniphier-proxstream2.dtsi
rename to arch/arm/dts/uniphier-pxs2.dtsi
index 609cbaa9d7c77cdef6df66168999dec1539554e4..b64107b3dd4af1a61f779d3d5fd3374c3b29800b 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier ProXstream2 SoC
+ * Device Tree Source for UniPhier PXs2 SoC
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,17 +10,17 @@
/include/ "uniphier-common32.dtsi"
/ {
- compatible = "socionext,proxstream2";
+ compatible = "socionext,uniphier-pxs2";
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -27,6 +28,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -34,6 +36,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
@@ -41,6 +44,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
};
@@ -361,6 +365,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
+ reset-names = "host", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 6>;
bus-width = <8>;
non-removable;
};
@@ -374,6 +380,8 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
+ reset-names = "host";
+ resets = <&mio_rst 0>;
bus-width = <4>;
};
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts
similarity index 76%
rename from arch/arm/dts/uniphier-ph1-sld3-ref.dts
rename to arch/arm/dts/uniphier-sld3-ref.dts
index 116e571e4e4cf83771790389e8ecb87f09604e89..f35500d4bba51e32711804fc1268d197110d29e1 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-sld3-ref.dts
@@ -1,19 +1,20 @@
/*
- * Device Tree Source for UniPhier PH1-sLD3 Reference Board
+ * Device Tree Source for UniPhier sLD3 Reference Board
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-sld3.dtsi"
+/include/ "uniphier-sld3.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-sLD3 Reference Board";
- compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3";
+ model = "UniPhier sLD3 Reference Board";
+ compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
similarity index 87%
rename from arch/arm/dts/uniphier-ph1-sld3.dtsi
rename to arch/arm/dts/uniphier-sld3.dtsi
index a554b086e8164bd1fcb81119c94d5a0dbf56a0c7..f5c54875348a7811a0afb0b6b86aee322c65d46c 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-sld3.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier PH1-sLD3 SoC
+ * Device Tree Source for UniPhier sLD3 SoC
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,26 +10,34 @@
/include/ "skeleton.dtsi"
/ {
- compatible = "socionext,ph1-sld3";
+ compatible = "socionext,uniphier-sld3";
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "socionext,uniphier-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
};
};
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
refclk: ref {
#clock-cells = <0>;
@@ -79,6 +88,18 @@
<0x20000100 0x100>;
};
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
@@ -280,6 +301,7 @@
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
@@ -317,6 +339,7 @@
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
+ resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>;
non-removable;
};
@@ -330,6 +353,7 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
+ resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
};
@@ -340,7 +364,9 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb1: usb@5a810100 {
@@ -350,7 +376,9 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
usb2: usb@5a820100 {
@@ -360,7 +388,9 @@
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
};
usb3: usb@5a830100 {
@@ -370,7 +400,9 @@
interrupts = <0 83 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
- clocks = <&mio_clk 7>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
+ <&mio_rst 15>;
};
soc-glue@5f800000 {
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts
similarity index 73%
rename from arch/arm/dts/uniphier-ph1-sld8-ref.dts
rename to arch/arm/dts/uniphier-sld8-ref.dts
index 9af012cab79ea0c048ddb16cfb8915982c53e6d2..6c0544b908ed2d90e7bba91a1f731a558855e770 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-sld8-ref.dts
@@ -1,19 +1,20 @@
/*
- * Device Tree Source for UniPhier PH1-sLD8 Reference Board
+ * Device Tree Source for UniPhier sLD8 Reference Board
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
-/include/ "uniphier-ph1-sld8.dtsi"
+/include/ "uniphier-sld8.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
- model = "UniPhier PH1-sLD8 Reference Board";
- compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8";
+ model = "UniPhier sLD8 Reference Board";
+ compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
memory {
device_type = "memory";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
similarity index 89%
rename from arch/arm/dts/uniphier-ph1-sld8.dtsi
rename to arch/arm/dts/uniphier-sld8.dtsi
index 1ecce5030f65eb5e9b7329d653c5c0d1a7aaf422..b8f6d674095778cffd63a1d26750ee330291f876 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -1,7 +1,8 @@
/*
- * Device Tree Source for UniPhier PH1-sLD8 SoC
+ * Device Tree Source for UniPhier sLD8 SoC
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@@ -9,7 +10,7 @@
/include/ "uniphier-common32.dtsi"
/ {
- compatible = "socionext,ph1-sld8";
+ compatible = "socionext,uniphier-sld8";
cpus {
#address-cells = <1>;
@@ -19,6 +20,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ enable-method = "psci";
next-level-cache = <&l2>;
};
};
@@ -223,6 +225,8 @@
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>;
};
@@ -235,6 +239,8 @@
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>;
+ reset-names = "host", "bridge", "hw-reset";
+ resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
bus-width = <8>;
non-removable;
};
@@ -246,7 +252,9 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb1: usb@5a810100 {
@@ -256,7 +264,9 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
usb2: usb@5a820100 {
@@ -266,7 +276,9 @@
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
};
aidet@61830000 {
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 79b1d2013a0e97c64f16729122acf44efc200d7a..059645171a721abb56edd43f5dad7ad3e9da320c 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -250,35 +250,35 @@ struct uniphier_board_id {
static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- { "socionext,ph1-sld3", &uniphier_sld3_data, },
+ { "socionext,uniphier-sld3", &uniphier_sld3_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- { "socionext,ph1-ld4", &uniphier_ld4_data, },
+ { "socionext,uniphier-ld4", &uniphier_ld4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- { "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, },
- { "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, },
- { "socionext,ph1-pro4", &uniphier_pro4_data, },
+ { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, },
+ { "socionext,uniphier-pro4", &uniphier_pro4_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- { "socionext,ph1-sld8", &uniphier_sld8_data, },
+ { "socionext,uniphier-sld8", &uniphier_sld8_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- { "socionext,ph1-pro5", &uniphier_pro5_data, },
+ { "socionext,uniphier-pro5", &uniphier_pro5_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
- { "socionext,proxstream2", &uniphier_pxs2_data, },
+ { "socionext,uniphier-pxs2", &uniphier_pxs2_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
- { "socionext,ph1-ld6b", &uniphier_ld6b_data, },
+ { "socionext,uniphier-ld6b", &uniphier_ld6b_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- { "socionext,ph1-ld11", &uniphier_ld11_data, },
+ { "socionext,uniphier-ld11", &uniphier_ld11_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- { "socionext,ph1-ld21", &uniphier_ld21_data, },
- { "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, },
- { "socionext,ph1-ld20", &uniphier_ld20_data, },
+ { "socionext,uniphier-ld21", &uniphier_ld21_data, },
+ { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, },
+ { "socionext,uniphier-ld20", &uniphier_ld20_data, },
#endif
};
diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c
index 8744d266e24a102c0042238b367e150d68a0a809..62b6927732a630402360cd4daae5ade7a87ebaa3 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld4.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -18,9 +20,6 @@ void uniphier_ld4_clk_init(void)
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c
index 8746d7df518dcc35b9141d5080ff81e1e1e1401f..92b73384abd29eda35c85b158eea5927b39a0620 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro4.c
@@ -1,5 +1,7 @@
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -22,9 +24,6 @@ void uniphier_pro4_clk_init(void)
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index 780fdd176f09a867f50b55d19b3c20b2419641ce..b0a4281f441984162817e1863f2191de5aeb2f96 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -63,9 +63,9 @@
#define SC_CLKCTRL7_UMC31 (1 << 1)
#define SC_CLKCTRL7_UMC30 (1 << 0)
-#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8080)
-#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8084)
-#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8088)
+#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
+#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
+#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
index 864e04e6913c199082c3ed9d9aa7566acd362ab8..c0ac5ac048cdcbade2599494b39af976ae79cbf7 100644
--- a/configs/uniphier_ld11_defconfig
+++ b/configs/uniphier_ld11_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index 3fe37586f0df32fb66dd4509e1a5c32cde131694..3e802d3e0841068c2a4f5799764c8ed5a6c93385 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD20=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index c18f04279d4311c1c2b84b5cf6a6e9fd39ce1bcd..b141561ab3ad44ac0db494efb06d2f3130dc11d2 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index 9441b053f1978cfc920bacd254d1912fb9de67fc..f71ef56019d1b1ec843d1d79ef1c6967c5cb82f9 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -6,7 +6,7 @@ CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index 0bf39f4e256b033a8216b4130b7f2ca7dffd19d7..ba3867f06ac9bfffd3e26b2404680ddfe2baa5a0 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index bd9c327e92c31f1893645a61abe93606100a99cb..3568f7a635e7233fcf3e5aaebfc89a8986f8783b 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/doc/README.uniphier b/doc/README.uniphier
index 49045a02188aa214bf1bcd555747e5bc28f92733..a42eaa97610b1e71ad78811ee1d665d35ac32d5c 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -2,74 +2,67 @@ U-Boot for UniPhier SoC family
==============================
-Tested toolchains
------------------
-
- (a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-)
-
- If you are building U-Boot on Ubuntu, its standard package is recommended.
- You can install it as follows:
+Recommended toolchains
+----------------------
- $ sudo apt-get install gcc-arm-linux-gnueabi-
-
- (b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-)
-
- You can download pre-built toolchains from:
+The UniPhir platform is well tested with Linaro toolchanis.
+You can download pre-built toolchains from:
http://www.linaro.org/downloads/
- (c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-)
-
- You can download pre-built toolchains from:
-
- ftp://www.kernel.org/pub/tools/crosstool/files/bin/
-
Compile the source
------------------
-PH1-sLD3 reference board:
+sLD3 reference board:
$ make uniphier_sld3_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-LD4 reference board:
+LD4 reference board:
$ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-sLD8 reference board:
+sLD8 reference board:
$ make uniphier_ld4_sld8_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref
-PH1-Pro4 reference board:
+Pro4 reference board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-Pro4 Ace board:
+Pro4 Ace board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-ace
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace
-PH1-Pro4 Sanji board:
+Pro4 Sanji board:
$ make uniphier_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-sanji
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji
-PH1-Pro5 4KBOX Board:
+Pro5 4KBOX Board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox
-ProXstream2 Gentil board:
+PXs2 Gentil board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil
-ProXstream2 Vodka board:
+PXs2 Vodka board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ $ make CROSS_COMPILE=arm-linux-gnueabihf-
-PH1-LD6b reference board:
+LD6b reference board:
$ make uniphier_pxs2_ld6b_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref
+ $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
+
+LD11 reference board:
+ $ make uniphier_ld11_defconfig
+ $ make CROSS_COMPILE=aarch64-linux-gnu-
-You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
-to use your favorite compiler.
+LD20 reference board:
+ $ make uniphier_ld20_defconfig
+ $ make CROSS_COMPILE=aarch64-linux-gnu-
+
+You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler.
Burn U-Boot images to NAND
@@ -119,6 +112,9 @@ UniPhier specific commands
- ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
shows the DDR PHY parameters set by the PHY training
+ - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
+ shows the DDR Multi PHY parameters set by the PHY training
+
Supported devices
-----------------
@@ -179,4 +175,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
--
Masahiro Yamada <yamada.masahiro@socionext.com>
-Feb. 2016
+Oct. 2016
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 0e90c01a9a94774aa6f6ab009ffc2ea413ce77cf..da3e3553895a3cba86f1dbc1d3075d4171845768 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -1,13 +1,10 @@
config CLK_UNIPHIER
- bool
+ bool "Clock driver for UniPhier SoCs"
+ depends on ARCH_UNIPHIER
select CLK
select SPL_CLK
-
-menu "Clock drivers for UniPhier SoCs"
- depends on CLK_UNIPHIER
-
-config CLK_UNIPHIER_MIO
- bool "Clock driver for UniPhier Media I/O block"
default y
-
-endmenu
+ help
+ Support for clock controllers on UniPhier SoCs.
+ Say Y if you want to control clocks provided by System Control
+ block, Media I/O block, Peripheral Block.
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index a3168f9bc1b718cbc0d0c166c0f4076cb8703b3c..ed623aa56f755cfc5276f764ab24ced69270733a 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -1,3 +1,2 @@
-obj-y += clk-uniphier-core.o
-
-obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o
+obj-y += clk-uniphier-core.o
+obj-y += clk-uniphier-mio.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 394832607ed81556901a2ab94c7431e7f7ac9aa3..8ad0242d2a77e83f8330fd9fb3e6b02d1cea16b7 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -6,11 +6,11 @@
*/
#include <common.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <clk-uclass.h>
-#include <dm/device.h>
#include "clk-uniphier.h"
@@ -18,136 +18,106 @@
* struct uniphier_clk_priv - private data for UniPhier clock driver
*
* @base: base address of the clock provider
- * @socdata: SoC specific data
+ * @data: SoC specific data
*/
struct uniphier_clk_priv {
void __iomem *base;
- const struct uniphier_clk_soc_data *socdata;
+ const struct uniphier_clk_data *data;
};
-int uniphier_clk_probe(struct udevice *dev)
+static int uniphier_clk_enable(struct clk *clk)
{
- struct uniphier_clk_priv *priv = dev_get_priv(dev);
- fdt_addr_t addr;
+ struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
+ unsigned long id = clk->id;
+ const struct uniphier_clk_gate_data *p;
- addr = dev_get_addr(dev->parent);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
+ for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) {
+ u32 val;
- priv->base = devm_ioremap(dev, addr, SZ_4K);
- if (!priv->base)
- return -ENOMEM;
+ if (p->id != id)
+ continue;
- priv->socdata = (void *)dev_get_driver_data(dev);
+ val = readl(priv->base + p->reg);
+ val |= BIT(p->bit);
+ writel(val, priv->base + p->reg);
- return 0;
+ return 0;
+ }
+
+ dev_err(priv->dev, "clk_id=%lu was not handled\n", id);
+ return -EINVAL;
}
-static int uniphier_clk_enable(struct clk *clk)
+static const struct uniphier_clk_mux_data *
+uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id)
{
- struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
- const struct uniphier_clk_gate_data *gate = priv->socdata->gate;
- unsigned int nr_gate = priv->socdata->nr_gate;
- void __iomem *reg;
- u32 mask, data, tmp;
- int i;
-
- for (i = 0; i < nr_gate; i++) {
- if (gate[i].index != clk->id)
- continue;
-
- reg = priv->base + gate[i].reg;
- mask = gate[i].mask;
- data = gate[i].data & mask;
+ const struct uniphier_clk_mux_data *p;
- tmp = readl(reg);
- tmp &= ~mask;
- tmp |= data & mask;
- debug("%s: %p: %08x\n", __func__, reg, tmp);
- writel(tmp, reg);
+ for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) {
+ if (p->id == id)
+ return p;
}
- return 0;
+ return NULL;
}
static ulong uniphier_clk_get_rate(struct clk *clk)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
- const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
- unsigned int nr_rdata = priv->socdata->nr_rate;
- void __iomem *reg;
- u32 mask, data;
- ulong matched_rate = 0;
+ const struct uniphier_clk_mux_data *mux;
+ u32 val;
int i;
- for (i = 0; i < nr_rdata; i++) {
- if (rdata[i].index != clk->id)
- continue;
+ mux = uniphier_clk_get_mux_data(priv, clk->id);
+ if (!mux)
+ return 0;
- if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
- return rdata[i].rate;
-
- reg = priv->base + rdata[i].reg;
- mask = rdata[i].mask;
- data = rdata[i].data & mask;
- if ((readl(reg) & mask) == data) {
- if (matched_rate && rdata[i].rate != matched_rate) {
- printf("failed to get clk rate for insane register values\n");
- return -EINVAL;
- }
- matched_rate = rdata[i].rate;
- }
- }
+ if (!mux->nr_muxs) /* fixed-rate */
+ return mux->rates[0];
+
+ val = readl(priv->base + mux->reg);
- debug("%s: rate = %lu\n", __func__, matched_rate);
+ for (i = 0; i < mux->nr_muxs; i++)
+ if ((mux->masks[i] & val) == mux->vals[i])
+ return mux->rates[i];
- return matched_rate;
+ return -EINVAL;
}
static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
{
struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
- const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
- unsigned int nr_rdata = priv->socdata->nr_rate;
- void __iomem *reg;
- u32 mask, data, tmp;
+ const struct uniphier_clk_mux_data *mux;
+ u32 val;
+ int i, best_rate_id = -1;
ulong best_rate = 0;
- int i;
- /* first, decide the best match rate */
- for (i = 0; i < nr_rdata; i++) {
- if (rdata[i].index != clk->id)
- continue;
+ mux = uniphier_clk_get_mux_data(priv, clk->id);
+ if (!mux)
+ return 0;
- if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
- return 0;
+ if (!mux->nr_muxs) /* fixed-rate */
+ return mux->rates[0];
- if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
- best_rate = rdata[i].rate;
+ /* first, decide the best match rate */
+ for (i = 0; i < mux->nr_muxs; i++) {
+ if (mux->rates[i] > best_rate && mux->rates[i] <= rate) {
+ best_rate = mux->rates[i];
+ best_rate_id = i;
+ }
}
- if (!best_rate)
- return -ENODEV;
+ if (best_rate_id < 0)
+ return -EINVAL;
+
+ val = readl(priv->base + mux->reg);
+ val &= ~mux->masks[best_rate_id];
+ val |= mux->vals[best_rate_id];
+ writel(val, priv->base + mux->reg);
debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
rate, best_rate);
- /* second, really set registers */
- for (i = 0; i < nr_rdata; i++) {
- if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
- continue;
-
- reg = priv->base + rdata[i].reg;
- mask = rdata[i].mask;
- data = rdata[i].data & mask;
-
- tmp = readl(reg);
- tmp &= ~mask;
- tmp |= data;
- debug("%s: %p: %08x\n", __func__, reg, tmp);
- writel(tmp, reg);
- }
-
return best_rate;
}
@@ -157,6 +127,24 @@ const struct clk_ops uniphier_clk_ops = {
.set_rate = uniphier_clk_set_rate,
};
+static int uniphier_clk_probe(struct udevice *dev)
+{
+ struct uniphier_clk_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev->parent);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = devm_ioremap(dev, addr, SZ_4K);
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->data = (void *)dev_get_driver_data(dev);
+
+ return 0;
+}
+
static const struct udevice_id uniphier_clk_match[] = {
{
.compatible = "socionext,uniphier-sld3-mio-clock",
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index c1e7197c1a867b6a5a100e7d984cd4faa7dd9e82..18e6856709255b297eebf4016187935083c5a396 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -5,136 +5,81 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <dm/device.h>
-
#include "clk-uniphier.h"
-#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x20 + 0x200 * (ch), \
- .mask = 0x00000100, \
- .data = 0x00000100, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110 + 0x200 * (ch), \
- .mask = 0x00000001, \
- .data = 0x00000001, \
- }
+#define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \
+ UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8)
-#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00000000, \
- .rate = 44444444, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00010000, \
- .rate = 33333333, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00020000, \
- .rate = 50000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00020000, \
- .rate = 66666666, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001000, \
- .rate = 100000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001100, \
- .rate = 40000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001200, \
- .rate = 25000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x30 + 0x200 * (ch), \
- .mask = 0x00031300, \
- .data = 0x00001300, \
- .rate = 22222222, \
- }
+#define UNIPHIER_MIO_CLK_USB2(id, ch) \
+ UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28)
-#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \
- { \
- .index = (idx), \
- .reg = 0x20 + 0x200 * (ch), \
- .mask = 0x30000000, \
- .data = 0x30000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110 + 0x200 * (ch), \
- .mask = 0x01000000, \
- .data = 0x01000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x114 + 0x200 * (ch), \
- .mask = 0x00000001, \
- .data = 0x00000001, \
- }
+#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \
+ UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29)
+
+#define UNIPHIER_MIO_CLK_DMAC(id) \
+ UNIPHIER_CLK_GATE((id), 0x20, 25)
-#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \
- { \
- .index = (idx), \
- .reg = 0x20, \
- .mask = 0x02000000, \
- .data = 0x02000000, \
- }, \
- { \
- .index = (idx), \
- .reg = 0x110, \
- .mask = 0x00020000, \
- .data = 0x00020000, \
+#define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \
+ { \
+ .id = (_id), \
+ .nr_muxs = 8, \
+ .reg = 0x30 + 0x200 * (ch), \
+ .masks = { \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ }, \
+ .vals = { \
+ 0x00000000, \
+ 0x00010000, \
+ 0x00020000, \
+ 0x00030000, \
+ 0x00001000, \
+ 0x00001100, \
+ 0x00001200, \
+ 0x00001300, \
+ }, \
+ .rates = { \
+ 44444444, \
+ 33333333, \
+ 50000000, \
+ 66666666, \
+ 100000000, \
+ 40000000, \
+ 25000000, \
+ 22222222, \
+ }, \
}
static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
- UNIPHIER_MIO_CLK_GATE_SD(0, 0),
- UNIPHIER_MIO_CLK_GATE_SD(1, 1),
- UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
- UNIPHIER_MIO_CLK_GATE_USB(0, 3),
- UNIPHIER_MIO_CLK_GATE_USB(1, 4),
- UNIPHIER_MIO_CLK_GATE_USB(2, 5),
- UNIPHIER_MIO_CLK_GATE_DMAC(6),
- UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
+ UNIPHIER_MIO_CLK_SD_GATE(0, 0),
+ UNIPHIER_MIO_CLK_SD_GATE(1, 1),
+ UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */
+ UNIPHIER_MIO_CLK_DMAC(7),
+ UNIPHIER_MIO_CLK_USB2(8, 0),
+ UNIPHIER_MIO_CLK_USB2(9, 1),
+ UNIPHIER_MIO_CLK_USB2(10, 2),
+ UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
+ UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
+ UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
+ UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
+ UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
+ UNIPHIER_CLK_END
};
-static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
- UNIPHIER_MIO_CLK_RATE_SD(0, 0),
- UNIPHIER_MIO_CLK_RATE_SD(1, 1),
- UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
+static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = {
+ UNIPHIER_MIO_CLK_SD_MUX(0, 0),
+ UNIPHIER_MIO_CLK_SD_MUX(1, 1),
+ UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */
+ UNIPHIER_CLK_END
};
-const struct uniphier_clk_soc_data uniphier_mio_clk_data = {
+const struct uniphier_clk_data uniphier_mio_clk_data = {
.gate = uniphier_mio_clk_gate,
- .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
- .rate = uniphier_mio_clk_rate,
- .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
+ .mux = uniphier_mio_clk_mux,
};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 0b60337205e79c596e476de5a5a87b408cfc97a8..f9a560ee73d355cb38bdb0cb0d6faf92bb3f8c7f 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -10,36 +10,46 @@
#include <linux/kernel.h>
+#define UNIPHIER_CLK_MAX_NR_MUXS 8
+
struct uniphier_clk_gate_data {
- int index;
+ unsigned int id;
unsigned int reg;
- u32 mask;
- u32 data;
+ unsigned int bit;
};
-struct uniphier_clk_rate_data {
- int index;
+struct uniphier_clk_mux_data {
+ unsigned int id;
+ unsigned int nr_muxs;
unsigned int reg;
-#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX
- u32 mask;
- u32 data;
- unsigned long rate;
+ unsigned int masks[UNIPHIER_CLK_MAX_NR_MUXS];
+ unsigned int vals[UNIPHIER_CLK_MAX_NR_MUXS];
+ unsigned long rates[UNIPHIER_CLK_MAX_NR_MUXS];
};
-struct uniphier_clk_soc_data {
+struct uniphier_clk_data {
const struct uniphier_clk_gate_data *gate;
- unsigned int nr_gate;
- const struct uniphier_clk_rate_data *rate;
- unsigned int nr_rate;
+ const struct uniphier_clk_mux_data *mux;
};
-#define UNIPHIER_CLK_FIXED_RATE(i, f) \
+#define UNIPHIER_CLK_ID_END (unsigned int)(-1)
+
+#define UNIPHIER_CLK_END \
+ { .id = UNIPHIER_CLK_ID_END }
+
+#define UNIPHIER_CLK_GATE(_id, _reg, _bit) \
+ { \
+ .id = (_id), \
+ .reg = (_reg), \
+ .bit = (_bit), \
+ }
+
+#define UNIPHIER_CLK_FIXED_RATE(_id, _rate) \
{ \
- .index = i, \
- .reg = UNIPHIER_CLK_RATE_IS_FIXED, \
- .rate = f, \
+ .id = (_id), \
+ .rates = {(_reg),}, \
}
-extern const struct uniphier_clk_soc_data uniphier_mio_clk_data;
+extern const struct uniphier_clk_data uniphier_mio_clk_data;
#endif /* __CLK_UNIPHIER_H__ */
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 5c3db2ab60541fbd4605862b8ee2ff132ba5c811..21e2d377b4c453176280ce781dd00103ed8a266c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -91,7 +91,12 @@ struct uniphier_pinctrl_socdata {
#define __UNIPHIER_PINMUX_FUNCTION(func) #func
#ifdef CONFIG_SPL_BUILD
-#define UNIPHIER_PINCTRL_GROUP(grp) { .name = NULL }
+ /*
+ * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
+ * suppressing "defined but not used" warnings.
+ */
+#define UNIPHIER_PINCTRL_GROUP(grp) \
+ { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
#define UNIPHIER_PINMUX_FUNCTION(func) NULL
#else
#define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 7331d1332432ab550a9f878b8eecfc4b6ab3a508..5be46e5c5a2e6063b36a51fc773a6fb271d8fd67 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -126,7 +126,6 @@
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* USB */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION