diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..18b6a2664349099f8f53bf1605d332518a971a21
--- /dev/null
+++ b/arch/arm/dts/tegra186.dtsi
@@ -0,0 +1,56 @@
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "nvidia,tegra186";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts =
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uarta: serial@3100000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03100000 0x0 0x10000>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sdhci@3460000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03460000 0x0 0x200>;
+ interrupts = <GIC_SPI 31 0x04>;
+ status = "disabled";
+ };
+
+ gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts =
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..aaecfc7ea6c593b4b9d843868aec2a3d1895383d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h
new file mode 100644
index 0000000000000000000000000000000000000000..8031f23873ef0709b1cc3d347c5e841b66e22e84
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/tegra.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */
+#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE 0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 616a1c3cf345cc69d8b9e75763a644af09c942e2..b18a12e34203e9d467d381a05e8e1d2eb36bd8b7 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -54,6 +54,11 @@ config TEGRA210
select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
+config TEGRA186
+ bool "Tegra186 family"
+ select TEGRA186_GPIO
+ select TEGRA_ARMV8_COMMON
+
endchoice
config TEGRA_DISCONNECT_UDC_ON_BOOT
@@ -77,5 +82,6 @@ source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
+source "arch/arm/mach-tegra/tegra186/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b2dbc6999c710ce90abb12bd1e176c19a1081a72..12ee1cd7495b48a9055e6bb6ff154df3ed1080cf 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_TEGRA186
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += cpu.o
@@ -30,9 +31,11 @@ obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
+endif
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA186) += tegra186/
obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
new file mode 100644
index 0000000000000000000000000000000000000000..f4b6152a79374b3f9d87090e9ff33b854f9b634c
--- /dev/null
+++ b/arch/arm/mach-tegra/board186.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = (1.5 * 1024 * 1024 * 1024);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+}
+
+int board_mmc_init(bd_t *bd)
+{
+ tegra_mmc_init();
+
+ return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..124d8e5835926d01eaff8dd7b35fee3fdcad5e1b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TEGRA186
+
+choice
+ prompt "Tegra186 board select"
+
+endchoice
+
+config SYS_SOC
+ default "tegra186"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..ce4610d8f809a999f5ade4d75a298b6b718de959
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -0,0 +1,8 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += ../arm64-mmu.o
+obj-y += ../board186.o
+obj-y += ../lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
new file mode 100644
index 0000000000000000000000000000000000000000..aa7b9d038a7e3be5bb1531f80477959e9a4fae5a
--- /dev/null
+++ b/include/configs/tegra186-common.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_TEXT_BASE 0x80080000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "pxefile_addr_r=0x90100000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+#endif