diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index a4934ef78a0f27de04d756e516512c5ca2cdb561..98991c688befb7fa7912dcd59769cae701f23374 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -17,6 +17,3 @@ obj-y += speed.o
obj-$(CONFIG_FSL_DIU_FB) += diu.o
obj-$(CONFIG_CMD_IDE) += ide.o
obj-$(CONFIG_PCI) += pci.o
-
-# Stub implementations of cache management functions for USB
-obj-$(CONFIG_USB_EHCI) += cache.o
diff --git a/arch/powerpc/cpu/mpc512x/cache.c b/arch/powerpc/cpu/mpc512x/cache.c
deleted file mode 100644
index 66384f988a6cb35cc48e5f947794cf86fc48331c..0000000000000000000000000000000000000000
--- a/arch/powerpc/cpu/mpc512x/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- *
- * This file contains stub implementation of
- * invalidate_dcache_range()
- * flush_dcache_range()
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
index d122b29aec56d2c05874c30909d7f2d36720bc9b..5c67e1d37d8ca858a1ac963e9ca0ca9dc1d72cd0 100644
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -7,7 +7,6 @@
extra-y = start.o
extra-y += traps.o
-obj-y += cache.o
obj-y += io.o
obj-y += firmware_sc_task_bestcomm.impl.o
obj-y += i2c.o
diff --git a/arch/powerpc/cpu/mpc5xxx/cache.c b/arch/powerpc/cpu/mpc5xxx/cache.c
deleted file mode 100644
index 5d674bce418c0b8f2b61a4b597e61f73492863f5..0000000000000000000000000000000000000000
--- a/arch/powerpc/cpu/mpc5xxx/cache.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file contains stub implementation of
- * invalidate_dcache_range()
- * flush_dcache_range()
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index cf9116274d43ffb739313b34f46ba7d9d246178e..a93cf13628a30756d9f07d387ff65467cedf7654 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -35,9 +35,6 @@ obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCIE) += pcie.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
-# Stub implementations of cache management functions for USB
-obj-y += cache.o
-
ifndef CONFIG_SYS_FSL_DDRC_GEN2
obj-y += spd_sdram.o
endif
diff --git a/arch/powerpc/cpu/mpc83xx/cache.c b/arch/powerpc/cpu/mpc83xx/cache.c
deleted file mode 100644
index 66384f988a6cb35cc48e5f947794cf86fc48331c..0000000000000000000000000000000000000000
--- a/arch/powerpc/cpu/mpc83xx/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- *
- * This file contains stub implementation of
- * invalidate_dcache_range()
- * flush_dcache_range()
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index adb5bd378ce5a56eac394122263de1b3c5eba937..aff5fdb5146f884dd6a02b72bc2b3254e5061453 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -122,15 +122,13 @@ config TARGET_T208XRDB
bool "Support T208xRDB"
select SUPPORT_SPL
-config TARGET_T4240EMU
- bool "Support T4240EMU"
-
config TARGET_T4240QDS
bool "Support T4240QDS"
select SUPPORT_SPL
config TARGET_T4240RDB
bool "Support T4240RDB"
+ select SUPPORT_SPL
config TARGET_CONTROLCENTERD
bool "Support controlcenterd"
@@ -153,6 +151,9 @@ config TARGET_XPEDITE537X
config TARGET_XPEDITE550X
bool "Support xpedite550x"
+config TARGET_UCP1020
+ bool "Support uCP1020"
+
endchoice
source "board/freescale/b4860qds/Kconfig"
@@ -194,5 +195,6 @@ source "board/stx/stxssa/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
source "board/xes/xpedite550x/Kconfig"
+source "board/Arcturus/ucp1020/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index b93158b9ed25490505483566f35215f3d785dfc2..65c26c093c04b1741b2c942797c1618112b6b9af 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -114,7 +114,4 @@ endif
obj-y += tlb.o
obj-y += traps.o
-# Stub implementations of cache management functions for USB
-obj-y += cache.o
-
endif # not minimal
diff --git a/arch/powerpc/cpu/mpc85xx/cache.c b/arch/powerpc/cpu/mpc85xx/cache.c
deleted file mode 100644
index 66384f988a6cb35cc48e5f947794cf86fc48331c..0000000000000000000000000000000000000000
--- a/arch/powerpc/cpu/mpc85xx/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- *
- * This file contains stub implementation of
- * invalidate_dcache_range()
- * flush_dcache_range()
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2d5ddf012b6b3a27c370e0bc3c65ad94c87e77d0..b368562a2451911182ce874c98bd540980996541 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -299,6 +299,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (has_erratum_a007798())
puts("Work-around for Erratum A007798 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
+ if (has_erratum_a004477())
+ puts("Work-around for Erratum A004477 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index ec3b2924b9d87c9651c5b25c9c1c2ca7974fa4c0..3777c6faa166142685e0364e4e23c82d010b3346 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -249,8 +249,13 @@ void fdt_fixup_qportals(void *blob)
#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
#endif
- const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
- int i = *ci;
+ const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+ int i;
+
+ if (!ci)
+ goto err;
+
+ i = *ci;
#ifdef CONFIG_SYS_DPAA_FMAN
int j;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 321ade24fe7d639f1723f2bcb8672167202167c4..d954fe2fd20cb6637d5b40f5c6ecfde90701451f 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -73,7 +73,8 @@ void get_sys_info(sys_info_t *sys_info)
[14] = 4, /* CC4 PPL / 4 */
};
uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@@ -453,6 +454,48 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#endif
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_PPC_T2080)
+#define ESDHC_CLK_SEL 0x00000007
+#define ESDHC_CLK_SHIFT 0
+#define ESDHC_CLK_RCWSR 15
+#else /* Support T1040 T1024 by now */
+#define ESDHC_CLK_SEL 0xe0000000
+#define ESDHC_CLK_SHIFT 29
+#define ESDHC_CLK_RCWSR 7
+#endif
+ rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
+ switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
+ break;
+ case 2:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
+ break;
+ case 3:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
+ break;
+#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
+ case 4:
+ sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
+ break;
+#if defined(CONFIG_PPC_T2080)
+ case 5:
+ sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
+ break;
+#endif
+ case 6:
+ sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
+ break;
+ case 7:
+ sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
+ break;
+#endif
+ default:
+ sys_info->freq_sdhc = 0;
+ printf("Error: Unknown SDHC peripheral clock select!\n");
+ }
+#endif
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
@@ -660,12 +703,16 @@ int get_clocks (void)
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
+#else
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
defined(CONFIG_P1014)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
+#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 28f04eefabb86e959e7ec113d9f10587446ab2e8..e61d8e0fc2b3e3da10cfec92275ea4fb0da4907f 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1664,41 +1664,46 @@ clear_bss:
*/
.globl trap_init
trap_init:
+ mflr r11
+ bl _GLOBAL_OFFSET_TABLE_-4
+ mflr r12
+
/* Update IVORs as per relocation */
mtspr IVPR,r3
- li r4,CriticalInput@l
+ lwz r4,CriticalInput@got(r12)
mtspr IVOR0,r4 /* 0: Critical input */
- li r4,MachineCheck@l
+ lwz r4,MachineCheck@got(r12)
mtspr IVOR1,r4 /* 1: Machine check */
- li r4,DataStorage@l
+ lwz r4,DataStorage@got(r12)
mtspr IVOR2,r4 /* 2: Data storage */
- li r4,InstStorage@l
+ lwz r4,InstStorage@got(r12)
mtspr IVOR3,r4 /* 3: Instruction storage */
- li r4,ExtInterrupt@l
+ lwz r4,ExtInterrupt@got(r12)
mtspr IVOR4,r4 /* 4: External interrupt */
- li r4,Alignment@l
+ lwz r4,Alignment@got(r12)
mtspr IVOR5,r4 /* 5: Alignment */
- li r4,ProgramCheck@l
+ lwz r4,ProgramCheck@got(r12)
mtspr IVOR6,r4 /* 6: Program check */
- li r4,FPUnavailable@l
+ lwz r4,FPUnavailable@got(r12)
mtspr IVOR7,r4 /* 7: floating point unavailable */
- li r4,SystemCall@l
+ lwz r4,SystemCall@got(r12)
mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
- li r4,Decrementer@l
+ lwz r4,Decrementer@got(r12)
mtspr IVOR10,r4 /* 10: Decrementer */
- li r4,IntervalTimer@l
+ lwz r4,IntervalTimer@got(r12)
mtspr IVOR11,r4 /* 11: Interval timer */
- li r4,WatchdogTimer@l
+ lwz r4,WatchdogTimer@got(r12)
mtspr IVOR12,r4 /* 12: Watchdog timer */
- li r4,DataTLBError@l
+ lwz r4,DataTLBError@got(r12)
mtspr IVOR13,r4 /* 13: Data TLB error */
- li r4,InstructionTLBError@l
+ lwz r4,InstructionTLBError@got(r12)
mtspr IVOR14,r4 /* 14: Instruction TLB error */
- li r4,DebugBreakpoint@l
+ lwz r4,DebugBreakpoint@got(r12)
mtspr IVOR15,r4 /* 15: Debug */
+ mtlr r11
blr
.globl unlock_ram_in_cache
diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S
index 536d9b9d73b55ce980b6727c39ba2a5285d6f7a1..34968c604d7b28bb7273b3f58db23c713f8b608f 100644
--- a/arch/powerpc/cpu/mpc86xx/cache.S
+++ b/arch/powerpc/cpu/mpc86xx/cache.S
@@ -114,51 +114,6 @@ _GLOBAL(clean_dcache_range)
sync /* wait for dcbst's to get to ram */
blr
-/*
- * Write any modified data cache blocks out to memory
- * and invalidate the corresponding instruction cache blocks.
- *
- * flush_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_dcache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,LG_CACHE_LINE_SIZE
- beqlr
- mtctr r4
-
- sync
-1: dcbf 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbf's to get to ram */
- blr
-
-/*
- * Like above, but invalidate the D-cache. This is used by the 8xx
- * to invalidate the cache so the PPC core doesn't get stale data
- * from the CPM (no cache snooping here :-).
- *
- * invalidate_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(invalidate_dcache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,LG_CACHE_LINE_SIZE
- beqlr
- mtctr r4
-
- sync
-1: dcbi 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbi's to get to ram */
- blr
-
/*
* Flush a particular page from the data cache to RAM.
* Note: this is necessary because the instruction cache does *not*
diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S
index 2714c2f9386aea4d337c59ccb0d5f8e34258dcd2..93e83662ee35b87f4bb0c4c845f337a298d8f123 100644
--- a/arch/powerpc/cpu/ppc4xx/cache.S
+++ b/arch/powerpc/cpu/ppc4xx/cache.S
@@ -73,49 +73,6 @@ _GLOBAL(clean_dcache_range)
sync /* wait for dcbst's to get to ram */
blr
-/*
- * Write any modified data cache blocks out to memory and invalidate them.
- * Does not invalidate the corresponding instruction cache blocks.
- *
- * flush_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_dcache_range)
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
-
-1: dcbf 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- blr
-
-/*
- * Like above, but invalidate the D-cache. This is used by the 8xx
- * to invalidate the cache so the PPC core doesn't get stale data
- * from the CPM (no cache snooping here :-).
- *
- * invalidate_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(invalidate_dcache_range)
- li r5,L1_CACHE_BYTES-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,L1_CACHE_SHIFT
- beqlr
- mtctr r4
-
-1: dcbi 0,r3
- addi r3,r3,L1_CACHE_BYTES
- bdnz 1b
- sync /* wait for dcbi's to get to ram */
- blr
-
/*
* 40x cores have 8K or 16K dcache and 32 byte line size.
* 44x has a 32K dcache and 32 byte line size.
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 8beed3037ab9de2045acf8fd5664ba4e65ebe8f3..71794a82fe13ffa986f652ef069e8f2b1c339056 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -12,4 +12,6 @@
#ifndef __ASM_ARCH_MX85XX_GPIO_H
#define __ASM_ARCH_MX85XX_GPIO_H
+#include <asm/mpc85xx_gpio.h>
+
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 69e05923f68c4e55db2d2c4429d33b44d1503e28..9d56bc17732dd547506536f2e9a6a784e03268a7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -163,6 +163,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -294,6 +295,7 @@
#define CONFIG_FSL_SATA_ERRATUM_A001
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_P1023)
#define CONFIG_MAX_CPUS 2
@@ -374,6 +376,7 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
@@ -591,6 +594,7 @@
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_BSC9132)
@@ -615,6 +619,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_A005434
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -723,6 +728,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
+#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
@@ -769,7 +775,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
@@ -785,6 +790,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
+ per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -817,7 +825,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
@@ -830,6 +837,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
+ per rcw field value */
#define CONFIG_QBMAN_CLK_DIV 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@@ -877,6 +886,9 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
+#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
+ per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 5be718b1626ae39b61678eddea85c7bc9a9aa346..8bee8ca998e9f452da6546bc56395c5f61ad831b 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -19,6 +19,7 @@
#define FSL_PCI_PBFR 0x44
#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PCIE_V3_CFG_RDY 0x1
#define FSL_PROG_IF_AGENT 0x1
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index c57d9c0fafbf1da2fe101525512fea78e29cae26..4090975bf5e79224b837bb5321d2bfe371e23805 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -15,6 +15,9 @@
struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
+#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
+ u8 sdhc_adapter;
+#endif
#endif
#if defined(CONFIG_8xx)
unsigned long brg_clk;
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 87bb4a092b86cabd7e6f1550bc4401514dde29f8..1d0dad4ccbf78acb2c212dac7295806b34290259 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -72,9 +72,10 @@ static inline int gpio_request(unsigned gpio, const char *label)
return 0;
}
-static inline void gpio_free(unsigned gpio)
+static inline int gpio_free(unsigned gpio)
{
/* Compatibility shim */
+ return 0;
}
static inline int gpio_direction_input(unsigned gpio)
@@ -97,12 +98,13 @@ static inline int gpio_get_value(unsigned gpio)
return !!mpc85xx_gpio_get(1U << gpio);
}
-static inline void gpio_set_value(unsigned gpio, int value)
+static inline int gpio_set_value(unsigned gpio, int value)
{
if (value)
mpc85xx_gpio_set_high(1U << gpio);
else
mpc85xx_gpio_set_low(1U << gpio);
+ return 0;
}
static inline int gpio_is_valid(int gpio)
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 349a1c198577b40c9065ea129009b87729978b99..b96dbc60e092598083e3d0fe0cbb4f6807a7fb0f 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -9,6 +9,9 @@
#include <config.h>
#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
@@ -54,3 +57,48 @@ ppcDcbz:
ppcSync:
sync
blr
+
+/*
+ * Write any modified data cache blocks out to memory and invalidate them.
+ * Does not invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_dcache_range)
+ li r5,L1_CACHE_BYTES-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,L1_CACHE_SHIFT
+ beqlr
+ mtctr r4
+
+1: dcbf 0,r3
+ addi r3,r3,L1_CACHE_BYTES
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ blr
+
+/*
+ * Like above, but invalidate the D-cache. This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(invalidate_dcache_range)
+ li r5,L1_CACHE_BYTES-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,L1_CACHE_SHIFT
+ beqlr
+ mtctr r4
+
+ sync
+1: dcbi 0,r3
+ addi r3,r3,L1_CACHE_BYTES
+ bdnz 1b
+ sync /* wait for dcbi's to get to ram */
+ blr
+
diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..feca03aeef723dddc79bfbdac3ac22ef83fdb5e3
--- /dev/null
+++ b/board/Arcturus/ucp1020/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_UCP1020
+
+config SYS_BOARD
+ string
+ default "ucp1020"
+
+config SYS_VENDOR
+ string
+ default "Arcturus"
+
+config SYS_CONFIG_NAME
+ string
+ default "UCP1020"
+
+config SPI_FLASH
+ bool
+ default y
+
+config SPI_PCI
+ bool
+ default y
+
+choice
+ prompt "Target image select"
+
+config TARGET_UCP1020_NOR
+ bool "NOR flash u-boot image"
+
+config TARGET_UCP1020_SPIFLASH
+ bool "SPI flash u-boot image"
+
+endchoice
+
+if TARGET_UCP1020_SPIFLASH
+config UCBOOT
+ bool
+ default y
+
+config SPIFLASH
+ bool
+ default y
+endif
+
+endif
diff --git a/board/Arcturus/ucp1020/MAINTAINERS b/board/Arcturus/ucp1020/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..e4a4718188f5d1b2d1d3550d16571b300680b1e7
--- /dev/null
+++ b/board/Arcturus/ucp1020/MAINTAINERS
@@ -0,0 +1,7 @@
+UCP1020 BOARD
+M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
+S: Maintained
+F: board/Arcturus/ucp1020/
+F: include/configs/UCP1020.h
+F: configs/UCP1020_defconfig
+F: configs/UCP1020_SPIFLASH_defconfig
diff --git a/board/Arcturus/ucp1020/Makefile b/board/Arcturus/ucp1020/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..35c88b98a9301315d369ad130839837e855d7e81
--- /dev/null
+++ b/board/Arcturus/ucp1020/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013-2015 Arcturus Networks, Inc.
+# based on board/freescale/p1_p2_rdb_pc/Makefile
+# original copyright follows:
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y += ucp1020.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += cmd_arc.o
+
+endif
diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README
new file mode 100644
index 0000000000000000000000000000000000000000..555c4ef79fe9ac595a3191df161fd22c6ab2ce77
--- /dev/null
+++ b/board/Arcturus/ucp1020/README
@@ -0,0 +1,54 @@
+The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
+product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
+DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
+
+Information on the generic product family can be found here:
+ http://www.arcturusnetworks.com/products/ucp1020
+
+The UCP1020 several configurable options
+========================================
+
+- the selection of populated phy(s):
+ KSZ9031 (current default for eTSEC 1 and 3)
+
+- the selection of boot location:
+ SPI Flash or NOR flash
+
+The UCP1020 includes 2 default configurations
+=============================================
+NOR boot image:
+ configs/UCP1020_defconfig
+SPI boot image:
+ configs/UCP1020_SPIFLASH_defconfig
+
+The UCP1020 adds an additional command in cmd_arc.c to access and program
+SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
+HW Addresses.
+
+
+Build example
+=============
+
+make distclean
+make UCP1020_defconfig
+make
+
+Default Scripts
+===============
+A default upgrade scripts is included in the default environment variable example:
+
+B$ run tftpflash
+
+Dual Environment
+================
+
+This build enables dual / failover environment environment.
+
+NOR Flash Partition declarations and scripts
+============================================
+Several scripts are available to allow TFTP of images and programming directly
+into defined NOR flash partitions. Examples:
+
+B$ run program0
+B$ run program1
+B$ run program2
diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c
new file mode 100644
index 0000000000000000000000000000000000000000..fa6b4853f9b063ce2d042f8618928d127f330a84
--- /dev/null
+++ b/board/Arcturus/ucp1020/cmd_arc.c
@@ -0,0 +1,231 @@
+/*
+ * Command for accessing Arcturus factory environment.
+ *
+ * Copyright 2013-2015 Arcturus Networks Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * by Oleksandr G Zhadan et al.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ *
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include <asm/io.h>
+
+#ifndef CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_SF_DEFAULT_SPEED 1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+# define CONFIG_SF_DEFAULT_MODE SPI_MODE0
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS 0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS 0
+#endif
+
+#define MAX_SERIAL_SIZE 15
+#define MAX_HWADDR_SIZE 17
+
+#define FIRM_ADDR1 (0x200 - sizeof(smac))
+#define FIRM_ADDR2 (0x400 - sizeof(smac))
+#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
+#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
+
+static struct spi_flash *flash;
+char smac[4][18];
+
+static int ishwaddr(char *hwaddr)
+{
+ if (strlen(hwaddr) == MAX_HWADDR_SIZE)
+ if (hwaddr[2] == ':' &&
+ hwaddr[5] == ':' &&
+ hwaddr[8] == ':' &&
+ hwaddr[11] == ':' &&
+ hwaddr[14] == ':')
+ return 0;
+ return -1;
+}
+
+static int set_arc_product(int argc, char *const argv[])
+{
+ int err = 0;
+ char *mystrerr = "ERROR: Failed to save factory info in spi location";
+
+ if (argc != 5)
+ return -1;
+
+ /* Check serial number */
+ if (strlen(argv[1]) != MAX_SERIAL_SIZE)
+ return -1;
+
+ /* Check HWaddrs */
+ if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
+ return -1;
+
+ strcpy(smac[3], argv[1]);
+ strcpy(smac[2], argv[2]);
+ strcpy(smac[1], argv[3]);
+ strcpy(smac[0], argv[4]);
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+
+ /*
+ * Save factory defaults
+ */
+
+ if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) {
+ printf("%s: %s [1]\n", __func__, mystrerr);
+ err++;
+ }
+ if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) {
+ printf("%s: %s [2]\n", __func__, mystrerr);
+ err++;
+ }
+
+ if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) {
+ printf("%s: %s [3]\n", __func__, mystrerr);
+ err++;
+ }
+
+ if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) {
+ printf("%s: %s [4]\n", __func__, mystrerr);
+ err++;
+ }
+
+ if (err == 4) {
+ printf("%s: %s [ALL]\n", __func__, mystrerr);
+ return -2;
+ }
+
+ return 0;
+}
+
+int get_arc_info(void)
+{
+ int location = 1;
+ char *myerr = "ERROR: Failed to read all 4 factory info spi locations";
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+
+ if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) {
+ location++;
+ if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) {
+ location++;
+ if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac),
+ smac)) {
+ location++;
+ if (spi_flash_read(flash, FIRM_ADDR4,
+ sizeof(smac), smac)) {
+ printf("%s: %s\n", __func__, myerr);
+ return -2;
+ }
+ }
+ }
+ }
+ if (smac[3][0] != 0) {
+ if (location > 1)
+ printf("Using region %d\n", location);
+ printf("SERIAL: ");
+ if (smac[3][0] == 0xFF) {
+ printf("\t<not found>\n");
+ } else {
+ printf("\t%s\n", smac[3]);
+ setenv("SERIAL", smac[3]);
+ }
+ }
+
+ if (strcmp(smac[2], "00:00:00:00:00:00") == 0)
+ return 0;
+
+ printf("HWADDR0:");
+ if (smac[2][0] == 0xFF) {
+ printf("\t<not found>\n");
+ } else {
+ char *ret = getenv("ethaddr");
+
+ if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
+ setenv("ethaddr", smac[2]);
+ printf("\t%s (factory)\n", smac[2]);
+ } else {
+ printf("\t%s\n", ret);
+ }
+ }
+
+ if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
+ setenv("eth1addr", smac[2]);
+ setenv("eth2addr", smac[2]);
+ return 0;
+ }
+
+ printf("HWADDR1:");
+ if (smac[1][0] == 0xFF) {
+ printf("\t<not found>\n");
+ } else {
+ char *ret = getenv("eth1addr");
+
+ if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
+ setenv("eth1addr", smac[1]);
+ printf("\t%s (factory)\n", smac[1]);
+ } else {
+ printf("\t%s\n", ret);
+ }
+ }
+
+ if (strcmp(smac[0], "00:00:00:00:00:00") == 0) {
+ setenv("eth2addr", smac[1]);
+ return 0;
+ }
+
+ printf("HWADDR2:");
+ if (smac[0][0] == 0xFF) {
+ printf("\t<not found>\n");
+ } else {
+ char *ret = getenv("eth2addr");
+
+ if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
+ setenv("eth2addr", smac[0]);
+ printf("\t%s (factory)\n", smac[0]);
+ } else {
+ printf("\t%s\n", ret);
+ }
+ }
+
+ return 0;
+}
+
+static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const char *cmd;
+ int ret = -1;
+
+ cmd = argv[1];
+ --argc;
+ ++argv;
+
+ if (strcmp(cmd, "product") == 0) {
+ ret = set_arc_product(argc, argv);
+ goto done;
+ }
+ if (strcmp(cmd, "info") == 0) {
+ ret = get_arc_info();
+ goto done;
+ }
+done:
+ if (ret == -1)
+ return CMD_RET_USAGE;
+
+ return ret;
+}
+
+U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
+ "Arcturus product command sub-system",
+ "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
+ "info - show Arcturus factory env\n\n");
diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c
new file mode 100644
index 0000000000000000000000000000000000000000..42fbae058d4b7dc3766aae2074725f8c98334b5a
--- /dev/null
+++ b/board/Arcturus/ucp1020/ddr.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1650,
+ .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
+ .taa_ps = 14050,
+ .twr_ps = 15000,
+ .trcd_ps = 13500,
+ .trrd_ps = 75000,
+ .trp_ps = 13500,
+ .tras_ps = 40000,
+ .trc_ps = 49500,
+ .trfc_ps = 160000,
+ .twtr_ps = 75000,
+ .trtp_ps = 75000,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 30000,
+};
+
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+ sys_info_t sysinfo;
+ char buf[32];
+ size_t ddr_size;
+ fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+ .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+ };
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freq_ddrbus));
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
+ return ddr_size;
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ if (pdimm->primary_sdram_width == 64)
+ popts->data_bus_width = 0;
+ else if (pdimm->primary_sdram_width == 32)
+ popts->data_bus_width = 1;
+ else
+ printf("Error in DDR bus width configuration!\n");
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c
new file mode 100644
index 0000000000000000000000000000000000000000..7d40905b5653d3fe577e1f6b11ceb9b041959cd5
--- /dev/null
+++ b/board/Arcturus/ucp1020/law.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_VSC7385_ENET
+ SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..236b0d0de5748686bd61c1ffb237d15a3c2dad56
--- /dev/null
+++ b/board/Arcturus/ucp1020/spl.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+ 66666000, 7499900, 83332500, 8999900,
+ 99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = bus_clk;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/Arcturus/ucp1020/spl_minimal.c b/board/Arcturus/ucp1020/spl_minimal.c
new file mode 100644
index 0000000000000000000000000000000000000000..5bdefb8a0d1d627a302d5d918f23826208e49f4e
--- /dev/null
+++ b/board/Arcturus/ucp1020/spl_minimal.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
+ * original copyright follows:
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c
new file mode 100644
index 0000000000000000000000000000000000000000..fd7134f5cf9c314ebb55c234fd54b41cfd7a5097
--- /dev/null
+++ b/board/Arcturus/ucp1020/tlb.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * based on board/freescale/p1_p2_rdb_pc/tlb.c
+ * original copyright follows:
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI memory 1.5G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O effective: 192K */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+ /* *I*G - VSC7385 Switch */
+ SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+#endif /* not SPL */
+
+#ifdef CONFIG_SYS_NAND_BASE
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+ /* *I*G - eSDHC/eSPI/NAND boot */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+
+#endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
new file mode 100644
index 0000000000000000000000000000000000000000..0fc2bac55d6a340fd472d225e18d80d1140027b2
--- /dev/null
+++ b/board/Arcturus/ucp1020/ucp1020.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * by Oleksandr G Zhadan et al.
+ * based on board/freescale/p1_p2_rdb_pc/spl.c
+ * original copyright follows:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <spi_flash.h>
+#include <mmc.h>
+#include <linux/ctype.h>
+#include <asm/fsl_serdes.h>
+#include <asm/gpio.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include "ucp1020.h"
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ /* TO DO: It's actially have to be in spi/ */
+}
+
+/*
+ * To be compatible with cmd_gpio
+ */
+int name_to_gpio(const char *name)
+{
+ int gpio = 31 - simple_strtoul(name, NULL, 10);
+
+ if (gpio < 16)
+ gpio = -1;
+
+ return gpio;
+}
+
+void board_gpio_init(void)
+{
+ int i;
+ char envname[8], *val;
+
+ for (i = 0; i < GPIO_MAX_NUM; i++) {
+ sprintf(envname, "GPIO%d", i);
+ val = getenv(envname);
+ if (val) {
+ char direction = toupper(val[0]);
+ char level = toupper(val[1]);
+
+ if (direction == 'I') {
+ gpio_direction_input(i);
+ } else {
+ if (direction == 'O') {
+ if (level == '1')
+ gpio_direction_output(i, 1);
+ else
+ gpio_direction_output(i, 0);
+ }
+ }
+ }
+ }
+
+ val = getenv("PCIE_OFF");
+ if (val) {
+ gpio_direction_input(GPIO_PCIE1_EN);
+ gpio_direction_input(GPIO_PCIE2_EN);
+ } else {
+ gpio_direction_output(GPIO_PCIE1_EN, 1);
+ gpio_direction_output(GPIO_PCIE2_EN, 1);
+ }
+
+ val = getenv("SDHC_CDWP_OFF");
+ if (!val) {
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+ }
+}
+
+int board_early_init_f(void)
+{
+ return 0; /* Just in case. Could be disable in config file */
+}
+
+int checkboard(void)
+{
+ printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
+ board_gpio_init();
+ printf("SD/MMC: 4-bit Mode\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#if defined(CONFIG_PHY_MICREL_KSZ9021)
+ int regval;
+ static int cnt;
+
+ if (cnt++ == 0)
+ printf("PHYs address [");
+
+ if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
+ regval =
+ ksz9021_phy_extended_read(phydev,
+ MII_KSZ9021_EXT_STRAP_STATUS);
+ /*
+ * min rx data delay
+ */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x6666);
+ /*
+ * max rx/tx clock delay, min rx/tx control
+ */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf6f6);
+ printf("0x%x", (regval & 0x1f));
+ } else {
+ printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
+ }
+ if (cnt == 3)
+ printf("] ");
+ else
+ printf(",");
+#endif
+
+#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
+ regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
+ if (regval >= 0)
+ printf(" (ADDR 0x%x) ", regval & 0x1f);
+#endif
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ static char newkernelargs[256];
+ static u8 id1[16];
+ static u8 id2;
+ struct mmc *mmc;
+ char *sval, *kval;
+
+ if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
+ printf("Error reading i2c IDT6V49205B information!\n");
+ } else {
+ printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
+ i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+ if (!(id1[1] & 0x02)) {
+ id1[1] |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
+ asm("nop; nop");
+ }
+ }
+
+ if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
+ printf("Error reading i2c NCT72 information!\n");
+ else
+ printf("NCT72(0x%x): ready\n", id2);
+
+ kval = getenv("kernelargs");
+
+ mmc = find_mmc_device(0);
+ if (mmc)
+ if (!mmc_init(mmc)) {
+ printf("MMC/SD card detected\n");
+ if (kval) {
+ int n = strlen(defkargs);
+ char *tmp = strstr(kval, defkargs);
+
+ *tmp = 0;
+ strcpy(newkernelargs, kval);
+ strcat(newkernelargs, " ");
+ strcat(newkernelargs, mmckargs);
+ strcat(newkernelargs, " ");
+ strcat(newkernelargs, &tmp[n]);
+ setenv("kernelargs", newkernelargs);
+ } else {
+ setenv("kernelargs", mmckargs);
+ }
+ }
+ get_arc_info();
+
+ if (kval) {
+ sval = getenv("SERIAL");
+ if (sval) {
+ strcpy(newkernelargs, "SN=");
+ strcat(newkernelargs, sval);
+ strcat(newkernelargs, " ");
+ strcat(newkernelargs, kval);
+ setenv("kernelargs", newkernelargs);
+ }
+ } else {
+ printf("Error reading kernelargs env variable!\n");
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+#ifdef CONFIG_TSEC2
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
+ puts("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+ }
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+ const char *soc_usb_compat = "fsl-usb2-dr";
+ int err, usb1_off, usb2_off;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ FT_FSL_PCI_SETUP;
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ /* Delete eLBC node as it is muxed with USB2 controller */
+ if (hwconfig("usb2")) {
+ const char *soc_elbc_compat = "fsl,p1020-elbc";
+ int off = fdt_node_offset_by_compatible(blob, -1,
+ soc_elbc_compat);
+ if (off < 0) {
+ printf
+ ("WARNING: could not find compatible node %s: %s\n",
+ soc_elbc_compat, fdt_strerror(off));
+ return off;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s\n",
+ soc_elbc_compat, fdt_strerror(err));
+ }
+ return err;
+ }
+#endif
+
+/* Delete USB2 node as it is muxed with eLBC */
+ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
+ if (usb1_off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ soc_usb_compat, fdt_strerror(usb1_off));
+ return usb1_off;
+ }
+ usb2_off =
+ fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
+ if (usb2_off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ soc_usb_compat, fdt_strerror(usb2_off));
+ return usb2_off;
+ }
+ err = fdt_del_node(blob, usb2_off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s.\n",
+ soc_usb_compat, fdt_strerror(err));
+ }
+ return 0;
+}
+#endif
diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h
new file mode 100644
index 0000000000000000000000000000000000000000..243459c44615080d132f2fa44e64afb3413191e8
--- /dev/null
+++ b/board/Arcturus/ucp1020/ucp1020.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * by Oleksandr G Zhadan et al.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __UCP1020_H__
+#define __UCP1020_H__
+
+#define GPIO0 31
+#define GPIO1 30
+#define GPIO2 29
+#define GPIO3 28
+#define GPIO4 27
+#define GPIO5 26
+#define GPIO6 25
+#define GPIO7 24
+#define GPIO8 23
+#define GPIO9 22
+#define GPIO10 21
+#define GPIO11 20
+#define GPIO12 19
+#define GPIO13 18
+#define GPIO14 17
+#define GPIO15 16
+#define GPIO_MAX_NUM 16
+
+#define GPIO_SDHC_CD GPIO8
+#define GPIO_SDHC_WP GPIO9
+#define GPIO_USB_PCTL0 GPIO10
+#define GPIO_PCIE1_EN GPIO11
+#define GPIO_PCIE2_EN GPIO10
+#define GPIO_USB_PCTL1 GPIO11
+
+#define GPIO_WD GPIO15
+
+static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
+static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
+
+int get_arc_info(void);
+
+#endif
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index 9e4132c64edc21437f59056b7c2ca4b8ba606071..e9cbd515a152cfd530c28a0e91b6e9ed384149a0 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -43,16 +43,16 @@ void fsl_dp_disable_console(void)
*/
static void dp_ddr_restore(void)
{
- volatile u64 *src, *dst;
+ u64 *src, *dst;
int i;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
/* get the address of ddr date from SPARECR3 */
- src = (u64 *)in_be32(&scfg->sparecr[2]);
- dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+ src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
+ dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
- *dst++ = *src++;
+ *dst-- = *src--;
flush_dcache();
}
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 52d20219ec01c8a378e873ef3f56eb0ef5711e3e..51ce9c328de10e8d21eb1741307bf37405b0c8f4 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -115,4 +115,18 @@ void qixis_write_i2c(unsigned int reg, u8 value);
qixis_write_i2c(offsetof(struct qixis, reg), value)
#endif
+/* Use for SDHC adapter card type identification and operation */
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#define QIXIS_SDID_MASK 0x07
+#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
+#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
+#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
+#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */
+#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */
+#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
+#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
+#define QIXIS_SDCLKIN 0x08
+#define QIXIS_SDCLKOUT 0x02
+#endif
+
#endif
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
index 7723f580db42b2ef91de6a5f06de8c2733a6bf5e..441d6a3e6142ed8903f3886fc03b460eb1397fc2 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -172,8 +172,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
if (port == FM1_DTSEC3) {
fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
- fdt_setprop(fdt, offset, "phy-connection-type",
- "rgmii", 5);
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "rgmii");
fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
@@ -207,7 +207,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
break;
}
fdt_delprop(fdt, offset, "phy-connection-type");
- fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "qsgmii");
fdt_status_okay_by_alias(fdt, "emi1_slot2");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* XFI interface */
@@ -219,7 +220,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
/* no PHY for XFI */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
- fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
+ fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
}
}
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
index dc554d4d3a89f10d59cd269a9909b8f060ef01bb..297e63a6eea0cef61bb98b4761067b6c6099f79b 100644
--- a/board/freescale/t102xrdb/MAINTAINERS
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -8,3 +8,8 @@ F: configs/T1024RDB_NAND_defconfig
F: configs/T1024RDB_SDCARD_defconfig
F: configs/T1024RDB_SPIFLASH_defconfig
F: configs/T1024RDB_SECURE_BOOT_defconfig
+F: configs/T1023RDB_defconfig
+F: configs/T1023RDB_NAND_defconfig
+F: configs/T1023RDB_SDCARD_defconfig
+F: configs/T1023RDB_SPIFLASH_defconfig
+F: configs/T1023RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index a0cf8f6fbfbb2a148b0fa57cf85fb64e2c13a989..052006610e6d3b211d317a517930bef02bd9e9a7 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += t102xrdb.o
-obj-y += cpld.o
+obj-$(CONFIG_T1024RDB) += cpld.o
obj-y += eth_t102xrdb.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index 2b17f50baef640ace397873cfe0b1085720975e5..922450e3c7bdeac666ae5bcacfbd3448bb49ff16 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -98,6 +98,30 @@ T1024RDB board Overview
- Four I2C ports
+T1023RDB board Overview
+-----------------------
+- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
+- CoreNet fabric supporting coherent and noncoherent transactions with
+ prioritization and bandwidth allocation
+- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
+- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
+- Ethernet interfaces:
+ - one 1G RGMII port on-board(RTL8211FS PHY)
+ - one 1G SGMII port on-board(RTL8211FS PHY)
+ - one 2.5G SGMII port on-board(AQR105 PHY)
+- PCIe: Two Mini-PCIe connectors on-board.
+- SerDes: 4 lanes up to 10.3125GHz
+- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
+- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
+- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
+- USB: one Type-A USB 2.0 port with internal PHY
+- eSDHC: support SD/MMC and eMMC card
+- 256Kbit M24256 I2C EEPROM
+- RTC: Real-time clock DS1339U on I2C bus
+- UART: one serial port on-board with RJ45 connector
+- Debugging: JTAG/COP for T1023 debugging
+
+
Memory map on T1024RDB
----------------------
Start Address End Address Description Size
@@ -117,29 +141,39 @@ Start Address End Address Description Size
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-128MB NOR Flash memory Map
---------------------------
+128MB NOR Flash Memory Layout
+-----------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
+0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
+0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
+0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
+0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
+0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
+0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
+0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
+0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
+0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
-T1024 Clock frequency
----------------------
+T1024/T1023 Clock frequency
+---------------------------
BIN Core DDR Platform FMan
Bin1: 1400MHz 1600MT/s 400MHz 700MHz
Bin2: 1200MHz 1600MT/s 400MHz 600MHz
@@ -155,16 +189,27 @@ Software configurations and board settings
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+ on T1024RDB:
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+ on T1023RDB:
+ set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
- via software: run command 'cpld reset altbank' in u-boot.
- via DIP-switch: set SW3[5:7] = '100'
+ on T1024RDB:
+ via software: run command 'cpld reset altbank' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
+ on T1023RDB:
+ via software: run command 'gpio vbank4' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
- via software: run command 'cpld reset' in u-boot.
- via DIP-Switch: set SW3[5:7] = '000'
+ on T1024RDB:
+ via software: run command 'cpld reset' in u-boot.
+ via DIP-Switch: set SW3[5:7] = '000'
+ on T1023RDB:
+ via software: run command 'gpio vbank0' in u-boot.
+ via DIP-switch: set SW3[5:7] = '000'
2. NAND Boot:
a. build PBL image for NAND boot
@@ -183,8 +228,11 @@ Software configurations and board settings
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
- => sf erase 0 f0000
+ => sf erase 0 100000
=> sf write 1000000 0 $filesize
+ => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+ => sf erase 100000 100000
+ => sf write 1000000 110000 20000
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
@@ -236,23 +284,34 @@ Start End Definition Size
0x200000 0x27FFFF QE Firmware 512KB(1 block)
+NAND Flash memory Map on T1023RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x15FFFF u-boot env 8KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+
+
SD Card memory Map on T1024RDB
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB
+0x920 0256 QE Firmware 128KB(only T1024RDB)
-SPI Flash memory Map on T1024RDB
+64MB SPI Flash memory Map on T102xRDB
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB
+0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
+0x300000 0x3FFFFF device tree 128KB
+0x400000 0x9FFFFF Linux kernel 6MB
+0xa00000 0x3FFFFFF rootfs 54MB
-For more details, please refer to T1024RDB Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+For more details, please refer to T1024RDB Reference Manual
+and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a2a8f4ccf0417f9932ebdbe38ea87e160e2dfe5b..adf9fd5f78b448cb010cb2a5493abe9b347570f4 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -135,8 +135,83 @@ found:
/* for DDR bus 32bit test on T1024 */
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
+
+#ifdef CONFIG_T1023RDB
+ popts->wrlvl_ctl_2 = 0x07070606;
+ popts->half_strength_driver_enable = 1;
+#endif
}
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 0x80000000,
+ .capacity = 0x80000000,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .bank_addr_bits = 2,
+ .bank_group_bits = 2,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+ .tckmin_x_ps = 938,
+ .tckmax_ps = 1500,
+ .caslat_x = 0x000DFA00,
+ .taa_ps = 13500,
+ .trcd_ps = 13500,
+ .trp_ps = 13500,
+ .tras_ps = 33000,
+ .trc_ps = 46500,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 25000,
+ .trrds_ps = 3700,
+ .trrdl_ps = 5300,
+ .tccdl_ps = 5355,
+ .refresh_rate_ps = 7800000,
+ .dq_mapping[0] = 0x0,
+ .dq_mapping[1] = 0x0,
+ .dq_mapping[2] = 0x0,
+ .dq_mapping[3] = 0x0,
+ .dq_mapping[4] = 0x0,
+ .dq_mapping[5] = 0x0,
+ .dq_mapping[6] = 0x0,
+ .dq_mapping[7] = 0x0,
+ .dq_mapping[8] = 0x0,
+ .dq_mapping[9] = 0x0,
+ .dq_mapping[10] = 0x0,
+ .dq_mapping[11] = 0x0,
+ .dq_mapping[12] = 0x0,
+ .dq_mapping[13] = 0x0,
+ .dq_mapping[14] = 0x0,
+ .dq_mapping[15] = 0x0,
+ .dq_mapping[16] = 0x0,
+ .dq_mapping[17] = 0x0,
+ .dq_mapping_ors = 1,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR4 on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
@@ -155,8 +230,9 @@ phys_size_t initdram(int board_type)
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
puts("Initializing....using SPD\n");
-
+#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index f611ff07e98cb8858995f5d67c10257ea6b44c2b..856ec6e227961d3be13f745ad55ffd82b8e45673 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -1,6 +1,8 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -56,6 +58,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
+#ifdef CONFIG_T1024RDB
case 0x95:
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -63,10 +66,17 @@ int board_eth_init(bd_t *bis)
/* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
+#endif
+ case 0x6a:
+ case 0x6b:
case 0x77:
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
+#ifdef CONFIG_T1023RDB
+ /* set the on-board 1G SGMII RTL8211F PHY */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
+#endif
break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
@@ -81,6 +91,14 @@ int board_eth_init(bd_t *bis)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
+ case PHY_INTERFACE_MODE_SGMII:
+#if defined(CONFIG_T1023RDB)
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+#elif defined(CONFIG_T1024RDB)
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+#endif
+ fm_info_set_mdio(i, dev);
+ break;
case PHY_INTERFACE_MODE_SGMII_2500:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
@@ -110,13 +128,16 @@ int board_eth_init(bd_t *bis)
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
- if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
- (port == FM1_DTSEC3)) {
+#if defined(CONFIG_T1024RDB)
+ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+ (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
+ (port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
- fdt_setprop(fdt, offset, "phy-connection-type",
- "sgmii-2500", 10);
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "sgmii-2500");
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
+#endif
}
void fdt_fixup_board_enet(void *fdt)
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fa781d61a5891363889abd69a16e46da4315ce08
--- /dev/null
+++ b/board/freescale/t102xrdb/t1023_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000e 00000000 00000000 00000000
+3b800003 00000012 e8104000 21000000
+00000000 00000000 00000000 00020800
+00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index e196f12ac7a16844a3633a9691b40b24dc79eb0a..f971976d73b3996a462dc9e9a89b5d265410aff2 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -18,11 +18,25 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
+#ifdef CONFIG_T1024RDB
#include "cpld.h"
+#endif
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_T1023RDB
+enum {
+ GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
+ GPIO1_EMMC_SEL,
+ GPIO1_VBANK0,
+ GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */
+ GPIO1_VBANK_MASK = 0x00008a00,
+ GPIO1_DIR_OUTPUT = 0x00028a00,
+ GPIO1_GET_VAL,
+};
+#endif
+
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
@@ -34,14 +48,17 @@ int checkboard(void)
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
- printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+#ifdef CONFIG_T1024RDB
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+#endif
+ printf("boot from ");
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
-#else
+#elif defined(CONFIG_T1024RDB)
u8 reg;
reg = CPLD_READ(flash_csr);
@@ -52,17 +69,25 @@ int checkboard(void)
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", reg);
}
+#elif defined(CONFIG_T1023RDB)
+#ifdef CONFIG_NAND
+ puts("NAND\n");
+#else
+ printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
+ GPIO1_VBANK4) >> 15 ? 4 : 0);
+#endif
#endif
puts("SERDES Reference Clocks:\n");
if (srds_s1 == 0x95)
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
else
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
return 0;
}
+#ifdef CONFIG_T1024RDB
static void board_mux_lane(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -82,6 +107,7 @@ static void board_mux_lane(void)
}
CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
}
+#endif
int board_early_init_f(void)
{
@@ -124,7 +150,9 @@ int board_early_init_r(void)
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+#ifdef CONFIG_T1024RDB
board_mux_lane();
+#endif
return 0;
}
@@ -170,3 +198,62 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
+
+
+#ifdef CONFIG_T1023RDB
+static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 gpioval;
+
+ setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
+ gpioval = in_be32(&pgpio->gpdat);
+
+ switch (ctrl_type) {
+ case GPIO1_SD_SEL:
+ gpioval |= GPIO1_SD_SEL;
+ break;
+ case GPIO1_EMMC_SEL:
+ gpioval &= ~GPIO1_SD_SEL;
+ break;
+ case GPIO1_VBANK0:
+ gpioval &= ~GPIO1_VBANK_MASK;
+ break;
+ case GPIO1_VBANK4:
+ gpioval &= ~GPIO1_VBANK_MASK;
+ gpioval |= GPIO1_VBANK4;
+ break;
+ case GPIO1_GET_VAL:
+ return gpioval;
+ default:
+ break;
+ }
+ out_be32(&pgpio->gpdat, gpioval);
+
+ return 0;
+}
+
+static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (!strcmp(argv[1], "vbank0"))
+ t1023rdb_gpio_ctrl(GPIO1_VBANK0);
+ else if (!strcmp(argv[1], "vbank4"))
+ t1023rdb_gpio_ctrl(GPIO1_VBANK4);
+ else if (!strcmp(argv[1], "sd"))
+ t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
+ else if (!strcmp(argv[1], "EMMC"))
+ t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
+ else
+ return CMD_RET_USAGE;
+ return 0;
+}
+
+U_BOOT_CMD(
+ gpio, 2, 0, gpio_cmd,
+ "for vbank0/vbank4/SD/eMMC switch control in runtime",
+ "command (e.g. gpio vbank4)"
+);
+#endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
index 2f23579b8f9e23ac37c123eac508a2b1ae1dd23e..3f5d85aa822ef501e0ed16e9488fc71a55196058 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -9,5 +9,7 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-
+#ifdef CONFIG_T1023RDB
+static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
+#endif
#endif
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 3f1533888ddf51acd9a0e3c9e2b40027268fa318..9bd5247563441487d9d54d0de38c7730ca5dfc92 100644
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST 0x04
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
index 59025eaf1e952d159502855abf01e7c89cb46512..8096ff9f3721c24797c1a7846aaf1304332d7487 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -10,7 +10,10 @@ aa55aa55 010e0100
#For T2080 v1.1
#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
-1206001b 15000000 00000000 00000000
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
66150002 00000000 e8104000 c1000000
00800000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index ad393dfc5c250ddc71999997596886ab8356443f..0c2c1c565bdd115ad1332cfd43598bf710c19330 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
int misc_init_r(void)
{
+ u8 reg;
+
+ /* Reset CS4315 PHY */
+ reg = CPLD_READ(reset_ctl);
+ reg |= CPLD_RSTCON_EDC_RST;
+ CPLD_WRITE(reset_ctl, reg);
+
return 0;
}
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
index ab34b9ef4c9e520b58196253647109415a51e688..27a64b64b9f787901be96ae651a71307c880010e 100644
--- a/board/freescale/t4qds/Kconfig
+++ b/board/freescale/t4qds/Kconfig
@@ -1,16 +1,3 @@
-if TARGET_T4240EMU
-
-config SYS_BOARD
- default "t4qds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T4240EMU"
-
-endif
-
if TARGET_T4240QDS
config SYS_BOARD
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
index f88ee7df9e685d7d90ea5061b4352d869fea874f..b15911364212a63ad81cc0ff69a4636a6dba48d2 100644
--- a/board/freescale/t4qds/MAINTAINERS
+++ b/board/freescale/t4qds/MAINTAINERS
@@ -1,16 +1,14 @@
T4QDS BOARD
-#M: -
+M: Shaohui Xie <Shaohui.Xie@freescale.com>
S: Maintained
F: board/freescale/t4qds/
F: include/configs/T4240QDS.h
F: configs/T4160QDS_defconfig
F: configs/T4160QDS_NAND_defconfig
F: configs/T4160QDS_SDCARD_defconfig
-F: configs/T4160QDS_SPIFLASH_defconfig
F: configs/T4240QDS_defconfig
F: configs/T4240QDS_NAND_defconfig
F: configs/T4240QDS_SDCARD_defconfig
-F: configs/T4240QDS_SPIFLASH_defconfig
F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
T4160QDS_SECURE_BOOT BOARD
@@ -18,9 +16,3 @@ M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/T4160QDS_SECURE_BOOT_defconfig
F: configs/T4240QDS_SECURE_BOOT_defconfig
-
-T4240EMU BOARD
-M: York Sun <yorksun@freescale.com>
-S: Maintained
-F: include/configs/T4240EMU.h
-F: configs/T4240EMU_defconfig
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 4e8e5cb8e9ae0168c58f05977d074b116eb65cc8..bd2c1f16222a1bd0a226cbed457b690936bfa4e8 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_T4240QDS) += t4240qds.o
-obj-$(CONFIG_T4240EMU) += t4240emu.o
obj-$(CONFIG_T4240QDS)+= eth.o
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 8183af78feb1f17c23d7e1b9b7b7c84394c30ea8..4d0e3c497db2a6cff4b5b6545e4509a33f3da185 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -25,7 +25,6 @@ struct board_specific_parameters {
* for each n_ranks group.
*/
-#ifdef CONFIG_T4240QDS
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
@@ -63,31 +62,6 @@ static const struct board_specific_parameters rdimm0[] = {
{}
};
-#else /* CONFIG_T4240EMU */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
- {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
- {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
- {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
- {}
-};
-#endif /* CONFIG_T4240EMU */
-
/*
* The three slots have slightly different timing. The center values are good
* for all slots. We use identical speed tables for them. In future use, if
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6f09a7bba2ad9dffbccbb14a98b6c450c59636ea..267494c8b3e84f82a8f63e889a0863bf1dc36e2a 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
#serdes protocol 1_27_5_11
-16070019 18101916 00000000 00000000
+1607001b 18101b16 00000000 00000000
04362858 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
index 845c1b6d66d5b63009cf4e55c5bf9cd19cec02ba..53ccabc0fb4e1341a0c352abeaff52463ce28849 100644
--- a/board/freescale/t4rdb/MAINTAINERS
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
F: configs/T4160RDB_defconfig
F: configs/T4240RDB_defconfig
+F: configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 3886e3ded107136fc257bf9a5d48c797c11efe17..83b55ee193460f4ad2bce1a6640ad05a312e7ece 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -4,10 +4,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
obj-$(CONFIG_T4240RDB) += t4240rdb.o
obj-y += cpld.o
-obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 5a43c1bc78fc5b860cbfe24665acc8485705837f..27b37b5cc42284c2bedc732da48bed95bcc601e8 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -108,11 +108,15 @@ phys_size_t initdram(int board_type)
puts("Initializing....using SPD\n");
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
- puts(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..68ecde7909729e9abfc46fd890d0efc8a3bf11c0
--- /dev/null
+++ b/board/freescale/t4rdb/spl.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+
+#include "t4rdb.h"
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nSD boot...\n");
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+ mmc_boot();
+}
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
index c9f8ced2a3b3a4e67eb2046601ba1a09dc9549a0..e7bb673e463b2a9bbfde7bca0d83762d8392794d 100644
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ b/board/freescale/t4rdb/t4_pbi.cfg
@@ -19,9 +19,6 @@
09000d00 00000000
09000d04 fff80000
09000d08 81000012
-#slow mdio clock
-095fc030 00008148
-095fd030 00808148
#Configure alternate space
09000010 00000000
09000014 ff000000
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index e46c7b25a55c0098530410ba649c43aabd957c62..282fea482435d76e876f1a89964c2a950459371a 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -2,6 +2,6 @@
aa55aa55 010e0100
#serdes protocol 27_55_1_9
16070019 18101916 00000000 00000000
-6c6e0848 00448c00 6c020000 f5000000
-00000000 ee0000ee 00000000 000287fc
-00000000 50000000 00000000 00000028
+6c6e0848 00448c00 ec020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index 474301e2a77e43d86adac3fa58237f2e7ee76d81..6a6b4b5cc13feaee680d9083e6e9fa1caa312e9e 100644
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -51,6 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -91,6 +92,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_16M, 1),
#endif
+#endif
+
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -111,6 +114,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 18, BOOKE_PAGESZ_2G, 1)
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..c3ba6a198b155ef8b99d3b51081db213ef702a78
--- /dev/null
+++ b/configs/T1023RDB_NAND_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..a2632aa2dc9bd740f1d764b828d333ac1a314bf5
--- /dev/null
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..c2e2d7ecac2d3a58df7a2e79e957fdd78b58da6d
--- /dev/null
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..202103cddb7e57b14b9d830a82efc83c6ab1214b
--- /dev/null
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..a839925fbc43e1b13bb0f823276d0ece5d15e69a
--- /dev/null
+++ b/configs/T1023RDB_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index efbd5402d3b101bc6e74fad4cf1f3196a9d91a8e..721419468f2f96a33f0f35e0425dd1fc4ca54d10 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -1,5 +1,5 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 65ae8d7cddd9f47219696960d149fb3282ea8268..9c3350593ce36dde80cf1cf35bc9d31412474ddd 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -1,5 +1,5 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index 83772600a1defa52e5645f104de0e97de41dba1a..be014170d9a55d1bc0d552c4ffae3f95f0d17e68 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -1,4 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 0b995730e6d389f7685713b873767a7ccf68ffe1..5a59000bcff4d7c6a33d4b94df3ac9a93fae9b5a 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -1,5 +1,5 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index e19e404bd1568171b3687d580581cb4c383cea2a..c22b3edbab8d28f5e36a6cfff137d45dbc9c7cfd 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -1,4 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
diff --git a/configs/T4160QDS_SPIFLASH_defconfig b/configs/T4160QDS_SPIFLASH_defconfig
deleted file mode 100644
index 6146b00fd1294b7c86ea2440a718cfd2cffae542..0000000000000000000000000000000000000000
--- a/configs/T4160QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
diff --git a/configs/T4240EMU_defconfig b/configs/T4240EMU_defconfig
deleted file mode 100644
index e95151b2311793d51339061e6bba049dfa82789d..0000000000000000000000000000000000000000
--- a/configs/T4240EMU_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240EMU=y
diff --git a/configs/T4240QDS_SPIFLASH_defconfig b/configs/T4240QDS_SPIFLASH_defconfig
deleted file mode 100644
index 14dc48a0b83b17e3b05c6f09d03ae184bfcda666..0000000000000000000000000000000000000000
--- a/configs/T4240QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240QDS=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..c17ce43f9efd7cea98dd488ad0612c6955d7ffb4
--- /dev/null
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240RDB=y
diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..2ffb8da3a50932f6078d942035979f868658b960
--- /dev/null
+++ b/configs/UCP1020_SPIFLASH_defconfig
@@ -0,0 +1,6 @@
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_UCP1020=y
+CONFIG_TARGET_UCP1020_SPIFLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_UCP1020=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..61de360fe38a4d625bbca64d542f2871e1b26e72
--- /dev/null
+++ b/configs/UCP1020_defconfig
@@ -0,0 +1,5 @@
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_UCP1020=y
+CONFIG_SPI_FLASH=y
+CONFIG_UCP1020=y
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index 619c6b2d07bcab8bd2486748ad3b5028059659b9..7e713875763e4a5a86e4934c7c33bb7c4b406efd 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -1,6 +1,24 @@
-CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
-CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
-CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
+Freescale esdhc-specific options
-Accessing ESDHC registers can be determined by ESDHC IP's endian
-mode or processor's endian mode.
+ - CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ Support Freescale adapter card type identification. This is implemented by
+ operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
+ Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot.
+
+ SDHC Card ID[0:2] Adapter Card Type
+ 0b000 reserved
+ 0b001 eMMC Card Rev4.5
+ 0b010 SD/MMC Legacy Card
+ 0b011 eMMC Card Rev4.4
+ 0b100 reserved
+ 0b101 MMC Card
+ 0b110 SD Card Rev2.0/3.0
+ 0b111 No card is present
+ - CONFIG_SYS_FSL_ESDHC_LE
+ ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
+ determined by ESDHC IP's endian mode or processor's endian mode.
+ - CONFIG_SYS_FSL_ESDHC_BE
+ ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
+ by ESDHC IP's endian mode or processor's endian mode.
+
+ - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index b9bc1654d38d01cd877a0be54116d0cb003ea7a5..c4719e6f3635b6396ea731c8c624199d17cdc335 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -506,11 +506,47 @@ static void set_sysctl(struct mmc *mmc, uint clock)
esdhc_setbits32(®s->sysctl, clk);
}
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+static void esdhc_clock_control(struct mmc *mmc, bool enable)
+{
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ u32 value;
+ u32 time_out;
+
+ value = esdhc_read32(®s->sysctl);
+
+ if (enable)
+ value |= SYSCTL_CKEN;
+ else
+ value &= ~SYSCTL_CKEN;
+
+ esdhc_write32(®s->sysctl, value);
+
+ time_out = 20;
+ value = PRSSTAT_SDSTB;
+ while (!(esdhc_read32(®s->prsstat) & value)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
+ break;
+ }
+ time_out--;
+ mdelay(1);
+ }
+}
+#endif
+
static void esdhc_set_ios(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ /* Select to use peripheral clock */
+ esdhc_clock_control(mmc, false);
+ esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
+ esdhc_clock_control(mmc, true);
+#endif
/* Set the clock speed */
set_sysctl(mmc, mmc->clock);
@@ -694,6 +730,39 @@ int fsl_esdhc_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, cfg);
}
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+void mmc_adapter_card_type_ident(void)
+{
+ u8 card_id;
+ u8 value;
+
+ card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
+ gd->arch.sdhc_adapter = card_id;
+
+ switch (card_id) {
+ case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
+ value = QIXIS_READ(brdcfg[5]);
+ value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
+ QIXIS_WRITE(brdcfg[5], value);
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
+ break;
+ case QIXIS_ESDHC_ADAPTER_TYPE_SD:
+ break;
+ case QIXIS_ESDHC_NO_ADAPTER:
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
@@ -707,9 +776,17 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
}
#endif
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+ gd->arch.sdhc_clk, 1);
+#else
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
gd->arch.sdhc_clk, 1);
-
+#endif
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ do_fixup_by_compat_u32(blob, compat, "adapter-type",
+ (u32)(gd->arch.sdhc_adapter), 1);
+#endif
do_fixup_by_compat(blob, compat, "status", "okay",
4 + 1, 1);
}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 3909e14e72f31b4a6f699a8407ffa6637763192b..79e6feeb13aca8a3ac55f92478307bf8dbfc8319 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1593,6 +1593,9 @@ int mmc_start_init(struct mmc *mmc)
if (mmc->has_init)
return 0;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ mmc_adapter_card_type_ident();
+#endif
board_mmc_power_init();
/* made sure it's not NULL earlier */
@@ -1744,6 +1747,9 @@ static void do_preinit(void)
list_for_each(entry, &mmc_devices) {
m = list_entry(entry, struct mmc, link);
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ mmc_set_preinit(m, 1);
+#endif
if (m->preinit)
mmc_start_init(m);
}
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 16dcf9ff617b736e357531d1c466c6abb26de82c..447a7001dbd986719aca1c39acbf0e5cd58dc80c 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -16,6 +16,9 @@ extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data);
extern int mmc_send_status(struct mmc *mmc, int timeout);
extern int mmc_set_blocklen(struct mmc *mmc, int len);
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+void mmc_adapter_card_type_ident(void);
+#endif
#ifndef CONFIG_SPL_BUILD
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 231b07573f5b15a35c472bbf8c6cfcb124166412..52792dcd5973895582220de9fc81fccacc1b4277 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
ltssm = (in_be32(&pci->pex_csr0)
& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
enabled = (ltssm == 0x11) ? 1 : 0;
+#ifdef CONFIG_FSL_PCIE_RESET
+ int i;
+ /* assert PCIe reset */
+ setbits_be32(&pci->pdb_stat, 0x08000000);
+ (void) in_be32(&pci->pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(&pci->pdb_stat, 0x08000000);
+ asm("sync;isync");
+ for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+ <ssm);
+ udelay(1000);
+ }
+#endif
} else {
/* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
/* enabled = ltssm >= PCI_LTSSM_L0; */
@@ -682,8 +697,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
if (pcie_cap != 0x0) {
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
+ u32 block_rev = in_be32(&pci->block_rev1);
/* PCIe - set CFG_READY bit of Configuration Ready Register */
- pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+ if (block_rev >= PEX_IP_BLK_REV_3_0)
+ setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
+ else
+ pci_hose_write_config_byte(hose, dev,
+ FSL_PCIE_CFG_RDY, 0x1);
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 2dca5244be9c15b87116b9e880c06e69d7c41927..5fd618df87bb876df1cb38d21c73185ef2463ee8 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
+ if (has_erratum_a004477()) {
+ /*
+ * When reset is issued while any ULPI transaction is ongoing
+ * then it may result to corruption of ULPI Function Control
+ * Register which eventually causes phy clock to enter low
+ * power mode which stops the clock. Thus delay is required
+ * before reset to let ongoing ULPI transaction complete.
+ */
+ udelay(1);
+ }
return 0;
}
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 84e8336a7247a93fd20307e6b3d1eee7570abf59..deff617ed4685deb547588892a3cf91e8b80d1be 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -11,6 +11,12 @@
#ifndef __T1024RDB_H
#define __T1024RDB_H
+#if defined(CONFIG_T1023RDB)
+#ifdef CONFIG_SPL
+#define CONFIG_SYS_NO_FLASH
+#endif
+#endif
+
/* High Level Configuration Options */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
@@ -35,7 +41,9 @@
#define CONFIG_ENV_OVERWRITE
/* support deep sleep */
+#ifdef CONFIG_PPC_T1024
#define CONFIG_DEEP_SLEEP
+#endif
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
@@ -43,7 +51,11 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
+#endif
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
@@ -177,7 +189,11 @@
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#if defined(CONFIG_T1024RDB)
#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_MMC
@@ -188,7 +204,11 @@
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
+#if defined(CONFIG_T1024RDB)
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
@@ -209,7 +229,7 @@ unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 66660000
+#define CONFIG_DDR_CLK_FREQ 100000000
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -224,6 +244,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
+#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
@@ -265,13 +286,18 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_FSL_DDR_INTERACTIVE
+#if defined(CONFIG_T1024RDB)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
-
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_SDRAM_SIZE 2048
+#endif
/*
* IFC Definitions
@@ -291,7 +317,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
+#endif
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
@@ -315,6 +346,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#ifdef CONFIG_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
@@ -336,6 +368,7 @@ unsigned long get_board_ddr_clk(void);
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
+#endif
/* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC
@@ -352,6 +385,7 @@ unsigned long get_board_ddr_clk(void);
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
@@ -359,9 +393,17 @@ unsigned long get_board_ddr_clk(void);
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
+ | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#endif
#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
@@ -381,8 +423,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
#if defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
@@ -536,7 +576,11 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SPI_FLASH_STMICRO
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_SPEED 10000000
@@ -736,8 +780,13 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
@@ -762,10 +811,16 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
+#if defined(CONFIG_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
-#define SGMII_PHY1_ADDR 0x2
+#define SGMII_AQR_PHY_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1
+#elif defined(CONFIG_T1023RDB)
+#define RGMII_PHY1_ADDR 0x1
+#define SGMII_RTK_PHY_ADDR 0x3
+#define SGMII_AQR_PHY_ADDR 0x2
+#endif
#endif
#ifdef CONFIG_FMAN_ENET
@@ -855,21 +910,23 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define __USB_PHY_TYPE utmi
#ifdef CONFIG_PPC_T1024
-#define CONFIG_BOARDNAME "t1024rdb"
+#define CONFIG_BOARDNAME t1024rdb
+#define BANK_INTLV cs0_cs1
#else
-#define CONFIG_BOARDNAME "t1023rdb"
+#define CONFIG_BOARDNAME t1023rdb
+#define BANK_INTLV null
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1\0" \
+ "bank_intlv=" __stringify(BANK_INTLV) "\0" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
"ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
"fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 046aa48baa1c0330c5efb3e0d67444eb146d5a15..bad3613b516819e667a7d1fc512c82bf02ec7bff 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -575,6 +575,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_RESET
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
@@ -756,6 +757,7 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
+#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
@@ -763,6 +765,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
#endif
diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h
deleted file mode 100644
index e8ba5d6b26b866b1847715c5cb0eb9b5fe9c9a85..0000000000000000000000000000000000000000
--- a/include/configs/T4240EMU.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * T4240 EMU board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_T4240EMU
-#define CONFIG_PHYS_64BIT
-
-#define CONFIG_SYS_NO_FLASH 1
-#define CONFIG_SYS_FSL_DDR_EMU 1
-#define CONFIG_SYS_FSL_NO_QIXIS 1
-#define CONFIG_SYS_FSL_NO_SERDES 1
-
-#include "t4qds.h"
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CACHE_FLUSH
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x2000
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-#define CONFIG_FSL_TBCLK_EXTRA_DIV 100
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_32 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-/* I2C */
-#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */
-#define CONFIG_SYS_FSL_I2C2_SPEED 4000000
-
-/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN
-
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#define CONFIG_BOOTDELAY 0
-
-/*
- * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
- * interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_PPC_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240emu/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=t4240emu/t4240emu.dtb\0" \
- "bdev=sda3\0"
-
-/*
- * For emulation this causes u-boot to jump to the start of the proof point
- * app code automatically
- */
-#define CONFIG_PROOF_POINTS \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "cpu 1 release 0x29000000 - - -;" \
- "cpu 2 release 0x29000000 - - -;" \
- "cpu 3 release 0x29000000 - - -;" \
- "cpu 4 release 0x29000000 - - -;" \
- "cpu 5 release 0x29000000 - - -;" \
- "cpu 6 release 0x29000000 - - -;" \
- "cpu 7 release 0x29000000 - - -;" \
- "go 0x29000000"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_LINUX \
- "errata;" \
- "setenv othbootargs ignore_loglevel;" \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 957a436374fbd3f790f412922003e8c28ad5ad9f..2a222493da533580f03110b965f562e94c26c4eb 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -21,11 +21,53 @@
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
+#ifndef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#else
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
+#define CONFIG_SPL_PAD_TO 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x28000
+#define RESET_VECTOR_OFFSET 0x27FFC
+#define BOOT_PAGE_OFFSET 0x27000
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#endif
+#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_DDR_ECC
@@ -84,7 +126,16 @@
/*
* Config the L3 Cache as L3 SRAM
*/
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE (512 << 10)
+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
@@ -112,7 +163,11 @@
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_R
@@ -135,7 +190,7 @@
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Serial Port - controlled on board with jumper J8
@@ -351,7 +406,7 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (512 * 1658)
+#define CONFIG_ENV_OFFSET (512 * 0x800)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
@@ -617,11 +672,11 @@ unsigned long get_board_ddr_clk(void);
#elif defined(CONFIG_SDCARD)
/*
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
new file mode 100644
index 0000000000000000000000000000000000000000..57e0c6c747ea0cf5e0880d6971ee24e84ecc5186
--- /dev/null
+++ b/include/configs/UCP1020.h
@@ -0,0 +1,1027 @@
+/*
+ * Copyright 2013-2015 Arcturus Networks, Inc.
+ * http://www.arcturusnetworks.com/products/ucp1020/
+ * based on include/configs/p1_p2_rdb_pc.h
+ * original copyright follows:
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * QorIQ uCP1020-xx boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_FSL_ELBC
+#define CONFIG_PCI
+#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#if defined(CONFIG_TARTGET_UCP1020T1)
+
+#define CONFIG_UCP1020_REV_1_3
+
+#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
+#define CONFIG_P1020
+
+#define CONFIG_TSEC_ENET
+#define CONFIG_TSEC1
+#define CONFIG_TSEC3
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
+#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
+#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
+#define CONFIG_IPADDR 10.80.41.229
+#define CONFIG_SERVERIP 10.80.41.227
+#define CONFIG_NETMASK 255.255.252.0
+#define CONFIG_ETHPRIME "eTSEC3"
+
+#ifndef CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH y
+#endif
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define CONFIG_MMC
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+
+#define CONFIG_LAST_STAGE_INIT
+
+#if !defined(CONFIG_DONGLE)
+#define CONFIG_SILENT_CONSOLE
+#endif
+
+#endif
+
+#if defined(CONFIG_TARGET_UCP1020)
+
+#define CONFIG_UCP1020
+#define CONFIG_UCP1020_REV_1_3
+
+#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
+#define CONFIG_P1020
+
+#define CONFIG_TSEC_ENET
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC3
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
+#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
+#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
+#define CONFIG_IPADDR 192.168.1.81
+#define CONFIG_IPADDR1 192.168.1.82
+#define CONFIG_IPADDR2 192.168.1.83
+#define CONFIG_SERVERIP 192.168.1.80
+#define CONFIG_GATEWAYIP 102.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#ifndef CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH y
+#endif
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define CONFIG_MMC
+#define CONFIG_SYS_L2_SIZE (256 << 10)
+
+#define CONFIG_LAST_STAGE_INIT
+
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500
+/* #define CONFIG_MPC85xx */
+
+#define CONFIG_MP
+
+#define CONFIG_FSL_LAW
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
+#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
+#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
+/*
+ * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For uCP1020 module:
+ * - only one ADM1021/NCT72
+ * - i2c addr 0x41
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT output disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
+ */
+#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
+ 0x02, 0, 1, 0, 85, 1, 0, 85} }
+
+#define CONFIG_CMD_DTT
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x1fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR 0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+ SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_DDR_ECC_ENABLE
+#define CONFIG_SYS_FSL_DDR3
+#ifndef CONFIG_DDR_ECC_ENABLE
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#endif
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+/* Default settings for DDR3 */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
+#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
+#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#ifdef CONFIG_DDR_ECC_ENABLE
+#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
+#else
+#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
+#endif
+#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
+#define CONFIG_SYS_DDR_TIMING_4 0x00220001
+#define CONFIG_SYS_DDR_TIMING_5 0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0 0x00330004
+#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
+#define CONFIG_SYS_DDR_MODE_1 0x40461520
+#define CONFIG_SYS_DDR_MODE_2 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
+ * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
+ * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
+ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
+ * (early boot only)
+ * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
+#define CONFIG_SYS_FLASH_BASE 0xec000000
+
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_PMC_BASE 0xff980000
+#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
+#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
+ BR_PS_8 | BR_V)
+#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+ OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+ OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
+#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_DS1337_NOOSC
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
+#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
+#define CONFIG_SYS_I2C_IDT6V49205B 0x69
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#define CONFIG_SPI_FLASH_SST 1
+#define CONFIG_SPI_FLASH_STMICRO 1
+#define CONFIG_SPI_FLASH_WINBOND 1
+#define CONFIG_CMD_SF 1
+#define CONFIG_CMD_SPI 1
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_ENV_FIT_UCBOOT
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+
+#else
+
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+
+#ifdef CONFIG_RAMBOOT_SPIFLASH
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
+#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
+#define CONFIG_ENV_SECT_SIZE 0x1000
+
+#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#endif
+
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
+#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#endif
+
+#endif
+
+#endif /* CONFIG_ENV_FIT_UCBOOT */
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_CRAMFS
+#define CONFIG_CRAMFS_CMDLINE
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_MMC_SPI
+#define CONFIG_CMD_MMC_SPI
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Misc Extra Settings */
+#define CONFIG_CMD_GPIO 1
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#if defined(CONFIG_UCP1020_REV_1_2)
+#define CONFIG_PHY_MICREL_KSZ9021
+#elif defined(CONFIG_UCP1020_REV_1_3)
+#define CONFIG_PHY_MICREL_KSZ9031
+#else
+#error "UCP1020 module revision is not defined !!!"
+#endif
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SERVERIP
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3_NAME "eTSEC3"
+
+#define TSEC1_PHY_ADDR 4
+#define TSEC2_PHY_ADDR 0
+#define TSEC2_PHY_ADDR_SGMII 0x00
+#define TSEC3_PHY_ADDR 6
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#endif
+
+#define CONFIG_HOSTNAME UCP1020
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+/*
+ * Autobooting
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "\x1b"
+#define DEBUG_BOOTKEYS 0
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#undef CONFIG_BOOTARGS
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
+ "press \"<Esc>\" to stop\n", bootdelay
+
+#define CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#if defined(CONFIG_DONGLE)
+
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"bootcmd=run prog_spi_mbrbootcramfs\0" \
+"bootfile=uImage\0" \
+"consoledev=ttyS0\0" \
+"cramfsfile=image.cramfs\0" \
+"dtbaddr=0x00c00000\0" \
+"dtbfile=image.dtb\0" \
+"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
+"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
+"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
+"fileaddr=0x01000000\0" \
+"filesize=0x00080000\0" \
+"flashmbr=sf probe 0; " \
+ "tftp $loadaddr $mbr; " \
+ "sf erase $mbr_offset +$filesize; " \
+ "sf write $loadaddr $mbr_offset $filesize\0" \
+"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
+ "protect off $nor_recoveryaddr +$filesize; " \
+ "erase $nor_recoveryaddr +$filesize; " \
+ "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
+ "protect on $nor_recoveryaddr +$filesize\0 " \
+"flashuboot=tftp $ubootaddr $ubootfile; " \
+ "protect off $nor_ubootaddr +$filesize; " \
+ "erase $nor_ubootaddr +$filesize; " \
+ "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
+ "protect on $nor_ubootaddr +$filesize\0 " \
+"flashworking=tftp $workingaddr $cramfsfile; " \
+ "protect off $nor_workingaddr +$filesize; " \
+ "erase $nor_workingaddr +$filesize; " \
+ "cp.b $workingaddr $nor_workingaddr $filesize; " \
+ "protect on $nor_workingaddr +$filesize\0 " \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
+"kerneladdr=0x01100000\0" \
+"kernelfile=uImage\0" \
+"loadaddr=0x01000000\0" \
+"mbr=uCP1020d.mbr\0" \
+"mbr_offset=0x00000000\0" \
+"mmbr=uCP1020Quiet.mbr\0" \
+"mmcpart=0:2\0" \
+"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
+ "mmc erase 1 1; " \
+ "mmc write $loadaddr 1 1\0" \
+"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
+ "mmc erase 0x40 0x400; " \
+ "mmc write $loadaddr 0x40 0x400\0" \
+"netdev=eth0\0" \
+"nor_recoveryaddr=0xEC0A0000\0" \
+"nor_ubootaddr=0xEFF80000\0" \
+"nor_workingaddr=0xECFA0000\0" \
+"norbootrecovery=setenv bootargs $recoverybootargs" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "run norloadrecovery; " \
+ "bootm $kerneladdr - $dtbaddr\0" \
+"norbootworking=setenv bootargs $workingbootargs" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "run norloadworking; " \
+ "bootm $kerneladdr - $dtbaddr\0" \
+"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
+ "setenv cramfsaddr $nor_recoveryaddr; " \
+ "cramfsload $dtbaddr $dtbfile; " \
+ "cramfsload $kerneladdr $kernelfile\0" \
+"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
+ "setenv cramfsaddr $nor_workingaddr; " \
+ "cramfsload $dtbaddr $dtbfile; " \
+ "cramfsload $kerneladdr $kernelfile\0" \
+"prog_spi_mbr=run spi__mbr\0" \
+"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
+"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
+ "run spi__cramfs\0" \
+"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $rootfsaddr $rootfsfile; " \
+ "tftp $loadaddr $kernelfile; " \
+ "tftp $dtbaddr $dtbfile; " \
+ "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
+"ramdisk_size=120000\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"recoveryaddr=0x02F00000\0" \
+"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
+"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
+ "mw.l 0xffe0f008 0x00400000\0" \
+"rootfsaddr=0x02F00000\0" \
+"rootfsfile=rootfs.ext2.gz.uboot\0" \
+"rootpath=/opt/nfsroot\0" \
+"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
+ "protect off 0xeC000000 +$filesize; " \
+ "erase 0xEC000000 +$filesize; " \
+ "cp.b $loadaddr 0xEC000000 $filesize; " \
+ "cmp.b $loadaddr 0xEC000000 $filesize; " \
+ "protect on 0xeC000000 +$filesize\0" \
+"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
+ "protect off 0xeFF80000 +$filesize; " \
+ "erase 0xEFF80000 +$filesize; " \
+ "cp.b $loadaddr 0xEFF80000 $filesize; " \
+ "cmp.b $loadaddr 0xEFF80000 $filesize; " \
+ "protect on 0xeFF80000 +$filesize\0" \
+"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
+ "sf probe 0; sf erase 0x8000 +$filesize; " \
+ "sf write $loadaddr 0x8000 $filesize\0" \
+"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
+ "protect off 0xec0a0000 +$filesize; " \
+ "erase 0xeC0A0000 +$filesize; " \
+ "cp.b $loadaddr 0xeC0A0000 $filesize; " \
+ "protect on 0xec0a0000 +$filesize\0" \
+"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
+ "sf probe 1; sf erase 0 +$filesize; " \
+ "sf write $loadaddr 0 $filesize\0" \
+"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
+ "sf probe 0; sf erase 0 +$filesize; " \
+ "sf write $loadaddr 0 $filesize\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
+"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
+"ubootaddr=0x01000000\0" \
+"ubootfile=u-boot.bin\0" \
+"ubootd=u-boot4dongle.bin\0" \
+"upgrade=run flashworking\0" \
+"usb_phy_type=ulpi\0 " \
+"workingaddr=0x02F00000\0" \
+"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
+
+#else
+
+#if defined(CONFIG_UCP1020T1)
+
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
+"bootfile=uImage\0" \
+"consoledev=ttyS0\0" \
+"cramfsfile=image.cramfs\0" \
+"dtbaddr=0x00c00000\0" \
+"dtbfile=image.dtb\0" \
+"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
+"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
+"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
+"fileaddr=0x01000000\0" \
+"filesize=0x00080000\0" \
+"flashmbr=sf probe 0; " \
+ "tftp $loadaddr $mbr; " \
+ "sf erase $mbr_offset +$filesize; " \
+ "sf write $loadaddr $mbr_offset $filesize\0" \
+"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
+ "protect off $nor_recoveryaddr +$filesize; " \
+ "erase $nor_recoveryaddr +$filesize; " \
+ "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
+ "protect on $nor_recoveryaddr +$filesize\0 " \
+"flashuboot=tftp $ubootaddr $ubootfile; " \
+ "protect off $nor_ubootaddr +$filesize; " \
+ "erase $nor_ubootaddr +$filesize; " \
+ "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
+ "protect on $nor_ubootaddr +$filesize\0 " \
+"flashworking=tftp $workingaddr $cramfsfile; " \
+ "protect off $nor_workingaddr +$filesize; " \
+ "erase $nor_workingaddr +$filesize; " \
+ "cp.b $workingaddr $nor_workingaddr $filesize; " \
+ "protect on $nor_workingaddr +$filesize\0 " \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
+"kerneladdr=0x01100000\0" \
+"kernelfile=uImage\0" \
+"loadaddr=0x01000000\0" \
+"mbr=uCP1020.mbr\0" \
+"mbr_offset=0x00000000\0" \
+"netdev=eth0\0" \
+"nor_recoveryaddr=0xEC0A0000\0" \
+"nor_ubootaddr=0xEFF80000\0" \
+"nor_workingaddr=0xECFA0000\0" \
+"norbootrecovery=setenv bootargs $recoverybootargs" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "run norloadrecovery; " \
+ "bootm $kerneladdr - $dtbaddr\0" \
+"norbootworking=setenv bootargs $workingbootargs" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "run norloadworking; " \
+ "bootm $kerneladdr - $dtbaddr\0" \
+"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
+ "setenv cramfsaddr $nor_recoveryaddr; " \
+ "cramfsload $dtbaddr $dtbfile; " \
+ "cramfsload $kerneladdr $kernelfile\0" \
+"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
+ "setenv cramfsaddr $nor_workingaddr; " \
+ "cramfsload $dtbaddr $dtbfile; " \
+ "cramfsload $kerneladdr $kernelfile\0" \
+"othbootargs=quiet\0" \
+"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $rootfsaddr $rootfsfile; " \
+ "tftp $loadaddr $kernelfile; " \
+ "tftp $dtbaddr $dtbfile; " \
+ "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
+"ramdisk_size=120000\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"recoveryaddr=0x02F00000\0" \
+"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
+"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
+ "mw.l 0xffe0f008 0x00400000\0" \
+"rootfsaddr=0x02F00000\0" \
+"rootfsfile=rootfs.ext2.gz.uboot\0" \
+"rootpath=/opt/nfsroot\0" \
+"silent=1\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
+"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
+"ubootaddr=0x01000000\0" \
+"ubootfile=u-boot.bin\0" \
+"upgrade=run flashworking\0" \
+"workingaddr=0x02F00000\0" \
+"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
+
+#else /* For Arcturus Modules */
+
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"bootcmd=run norkernel\0" \
+"bootfile=uImage\0" \
+"consoledev=ttyS0\0" \
+"dtbaddr=0x00c00000\0" \
+"dtbfile=image.dtb\0" \
+"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
+"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
+"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
+"fileaddr=0x01000000\0" \
+"filesize=0x00080000\0" \
+"flashmbr=sf probe 0; " \
+ "tftp $loadaddr $mbr; " \
+ "sf erase $mbr_offset +$filesize; " \
+ "sf write $loadaddr $mbr_offset $filesize\0" \
+"flashuboot=tftp $loadaddr $ubootfile; " \
+ "protect off $nor_ubootaddr0 +$filesize; " \
+ "erase $nor_ubootaddr0 +$filesize; " \
+ "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
+ "protect on $nor_ubootaddr0 +$filesize; " \
+ "protect off $nor_ubootaddr1 +$filesize; " \
+ "erase $nor_ubootaddr1 +$filesize; " \
+ "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
+ "protect on $nor_ubootaddr1 +$filesize\0 " \
+"format0=protect off $part0base +$part0size; " \
+ "erase $part0base +$part0size\0" \
+"format1=protect off $part1base +$part1size; " \
+ "erase $part1base +$part1size\0" \
+"format2=protect off $part2base +$part2size; " \
+ "erase $part2base +$part2size\0" \
+"format3=protect off $part3base +$part3size; " \
+ "erase $part3base +$part3size\0" \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
+"kerneladdr=0x01100000\0" \
+"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
+"kernelfile=uImage\0" \
+"loadaddr=0x01000000\0" \
+"mbr=uCP1020.mbr\0" \
+"mbr_offset=0x00000000\0" \
+"netdev=eth0\0" \
+"nor_ubootaddr0=0xEC000000\0" \
+"nor_ubootaddr1=0xEFF80000\0" \
+"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
+ "run norkernelload; " \
+ "bootm $kerneladdr - $dtbaddr\0" \
+"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
+ "setenv cramfsaddr $part0base; " \
+ "cramfsload $dtbaddr $dtbfile; " \
+ "cramfsload $kerneladdr $kernelfile\0" \
+"part0base=0xEC100000\0" \
+"part0size=0x00700000\0" \
+"part1base=0xEC800000\0" \
+"part1size=0x02000000\0" \
+"part2base=0xEE800000\0" \
+"part2size=0x00800000\0" \
+"part3base=0xEF000000\0" \
+"part3size=0x00F80000\0" \
+"partENVbase=0xEC080000\0" \
+"partENVsize=0x00080000\0" \
+"program0=tftp part0-000000.bin; " \
+ "protect off $part0base +$filesize; " \
+ "erase $part0base +$filesize; " \
+ "cp.b $loadaddr $part0base $filesize; " \
+ "echo Verifying...; " \
+ "cmp.b $loadaddr $part0base $filesize\0" \
+"program1=tftp part1-000000.bin; " \
+ "protect off $part1base +$filesize; " \
+ "erase $part1base +$filesize; " \
+ "cp.b $loadaddr $part1base $filesize; " \
+ "echo Verifying...; " \
+ "cmp.b $loadaddr $part1base $filesize\0" \
+"program2=tftp part2-000000.bin; " \
+ "protect off $part2base +$filesize; " \
+ "erase $part2base +$filesize; " \
+ "cp.b $loadaddr $part2base $filesize; " \
+ "echo Verifying...; " \
+ "cmp.b $loadaddr $part2base $filesize\0" \
+"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
+ " console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $rootfsaddr $rootfsfile; " \
+ "tftp $loadaddr $kernelfile; " \
+ "tftp $dtbaddr $dtbfile; " \
+ "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
+"ramdisk_size=120000\0" \
+"ramdiskfile=rootfs.ext2.gz.uboot\0" \
+"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
+ "mw.l 0xffe0f008 0x00400000\0" \
+"rootfsaddr=0x02F00000\0" \
+"rootfsfile=rootfs.ext2.gz.uboot\0" \
+"rootpath=/opt/nfsroot\0" \
+"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
+ "sf probe 0; sf erase 0 +$filesize; " \
+ "sf write $loadaddr 0 $filesize\0" \
+"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
+ "protect off 0xeC000000 +$filesize; " \
+ "erase 0xEC000000 +$filesize; " \
+ "cp.b $loadaddr 0xEC000000 $filesize; " \
+ "cmp.b $loadaddr 0xEC000000 $filesize; " \
+ "protect on 0xeC000000 +$filesize\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
+"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
+"ubootfile=u-boot.bin\0" \
+"upgrade=run flashuboot\0" \
+"usb_phy_type=ulpi\0 " \
+"boot_nfs= " \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr\0" \
+"boot_hd = " \
+ "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "usb start;" \
+ "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
+ "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
+ "bootm $loadaddr - $fdtaddr\0" \
+"boot_usb_fat = " \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs " \
+ "ramdisk_size=$ramdisk_size;" \
+ "usb start;" \
+ "fatload usb 0:2 $loadaddr $bootfile;" \
+ "fatload usb 0:2 $fdtaddr $fdtfile;" \
+ "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
+"boot_usb_ext2 = " \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs " \
+ "ramdisk_size=$ramdisk_size;" \
+ "usb start;" \
+ "ext2load usb 0:4 $loadaddr $bootfile;" \
+ "ext2load usb 0:4 $fdtaddr $fdtfile;" \
+ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
+"boot_nor = " \
+ "setenv bootargs root=/dev/$jffs2nor rw " \
+ "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
+ "bootm $norbootaddr - $norfdtaddr\0 " \
+"boot_ram = " \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs " \
+ "ramdisk_size=$ramdisk_size;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
+
+#endif
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/e500.h b/include/e500.h
index 255f46bf1e54c0ac98c46e35e20997819eb184a9..1acf7784dfc9ea04be7a5f803dbd39778a2c9ea5 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -18,6 +18,7 @@ typedef struct
unsigned long freq_ddrbus;
unsigned long freq_localbus;
unsigned long freq_qe;
+ unsigned long freq_sdhc;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 41bf05be4c042a6c9f86b16db7b5731b316000b9..0d00b7dfdbc5969bfd047cbacca57451a7756060 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -16,6 +16,10 @@
/* needed for the mmc_cfg definition */
#include <mmc.h>
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#include "../board/freescale/common/qixis.h"
+#endif
+
/* FSL eSDHC-specific constants */
#define SYSCTL 0x0002e02c
#define SYSCTL_INITA 0x08000000
@@ -74,6 +78,9 @@
#define IRQSTATEN_TC (0x00000002)
#define IRQSTATEN_CC (0x00000001)
+#define ESDHCCTL 0x0002e40c
+#define ESDHCCTL_PCS (0x00080000)
+
#define PRSSTAT 0x0002e024
#define PRSSTAT_DAT0 (0x01000000)
#define PRSSTAT_CLSL (0x00800000)
@@ -82,6 +89,7 @@
#define PRSSTAT_CINS (0x00010000)
#define PRSSTAT_BREN (0x00000800)
#define PRSSTAT_BWEN (0x00000400)
+#define PRSSTAT_SDSTB (0X00000008)
#define PRSSTAT_DLA (0x00000004)
#define PRSSTAT_CICHB (0x00000002)
#define PRSSTAT_CIDHB (0x00000001)
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 33d9f030960c27117e754ec49b51390e8ad2936a..8e3ddedfad1b71bf5ce0c90f4001734eb6e85891 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -209,6 +209,30 @@ static inline bool has_erratum_a005697(void)
return false;
}
+static inline bool has_erratum_a004477(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P1022:
+ case SVR_9131:
+ case SVR_9132:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ case SVR_P2020:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
+ IS_SVR_REV(svr, 2, 1);
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P4080:
+ return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+ }
+
+ return false;
+}
#else
static inline bool has_dual_phy(void)
{
@@ -239,5 +263,10 @@ static inline bool has_erratum_a005697(void)
{
return false;
}
+
+static inline bool has_erratum_a004477(void)
+{
+ return false;
+}
#endif
#endif /*_ASM_FSL_USB_H_ */