diff --git a/common/image.c b/common/image.c
index f7e8606ccad94ae94d7f1f9594c7942c184bc92c..d7fcd1db21b3cb4a448b07c108536b00ce69c87b 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1563,7 +1563,7 @@ int boot_get_fdt (int flag, int argc, char *argv[], bootm_headers_t *images,
 	*of_flat_tree = fdt_blob;
 	*of_size = be32_to_cpu (fdt_totalsize (fdt_blob));
 	debug ("   of_flat_tree at 0x%08lx size 0x%08lx\n",
-			*of_flat_tree, *of_size);
+			(ulong)*of_flat_tree, *of_size);
 
 	return 0;
 
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index 06d4d8b7342f477baaca9b1bd8f04c86694de9ce..d702ca6e4c2bcf1d7023130bf2b8981e77cc48a2 100644
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -48,29 +48,29 @@ int interrupt_init_cpu(unsigned long *decrementer_count)
 
 #ifdef CONFIG_INTERRUPTS
 	pic->iivpr1 = 0x810001;	/* 50220 enable ecm interrupts */
-	debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
+	debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
 
 	pic->iivpr2 = 0x810002;	/* 50240 enable ddr interrupts */
-	debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2);
+	debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
 
 	pic->iivpr3 = 0x810003;	/* 50260 enable lbc interrupts */
-	debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3);
+	debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
 
 #ifdef CONFIG_PCI1
 	pic->iivpr8 = 0x810008;	/* enable pci1 interrupts */
-	debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8);
+	debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
 #endif
 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
 	pic->iivpr9 = 0x810009;	/* enable pci1 interrupts */
-	debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9);
+	debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
 #endif
 #ifdef CONFIG_PCIE1
 	pic->iivpr10 = 0x81000a;	/* enable pcie1 interrupts */
-	debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10);
+	debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
 #endif
 #ifdef CONFIG_PCIE3
 	pic->iivpr11 = 0x81000b;	/* enable pcie3 interrupts */
-	debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11);
+	debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
 #endif
 
 	pic->ctpr=0;		/* 40080 clear current task priority register */
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 75676b5b9e8bd9d88d2e3ce0b139cb070b29298e..ec5e4daf88f1b09838f4a425f4742fe7acb1024e 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -37,6 +37,11 @@ __secondary_start_page:
 	li	r3,0x201
 	mtspr	SPRN_BUCSR,r3
 
+	/* Ensure TB is 0 */
+	li	r3,0
+	mttbl	r3
+	mttbu	r3
+
 	/* Enable/invalidate the I-Cache */
 	mfspr	r0,SPRN_L1CSR1
 	ori	r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 03ea2d040d7a3fda49cb6403b4f37e20b55a32bc..a74321d5c0eb2356b7a36a4b99d2b4e121973633 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -516,7 +516,7 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect,
 		retval = (flash_read16(addr) == cword.w);
 		break;
 	case FLASH_CFI_32BIT:
-		debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l);
+		debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
 		retval = (flash_read32(addr) == cword.l);
 		break;
 	case FLASH_CFI_64BIT: