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Yung-Ching LIN authored
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: default avatarKen Lin <yungching0725@gmail.com>
Acked-by: default avatarAkshay Bhat <akshay.bhat@timesys.com>
fab70acf
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Name Last commit Last update
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dms-ba16
som-db5800-som-6867
Kconfig