- 30 Jul, 2020 1 commit
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Maximilian Adducchio authored
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- 08 Jul, 2020 1 commit
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Frieder Schrempf authored
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- 22 Oct, 2019 15 commits
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Frieder Schrempf authored
Initially to detect the flash, DDR mode is not used so the TDH bits need to be cleared. In case of booting from QSPI, the BootROM might have left the TDH bits set, so we need to clear them actively. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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Ye Li authored
The write data size can be overwritten by writing to the IDATSZ field of IPCR register. Since the driver always updates the IDATSZ in page program operation. Set the LUT data size to 0 to align the codes with iMX. Signed-off-by:
Ye Li <ye.li@nxp.com>
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Ye Li authored
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller is updated to have TDH field in FLSHCR register. According to reference manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX DDR delay logic won't be enabled. Another issue in DDR mode is the MCR register will be overwritten in every read/write/erase operation. This causes DDR_EN been cleared while TDH=1, then no clk2x output for TX data shift and all operations will fail. Signed-off-by:
Ye Li <ye.li@nxp.com>
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Thomas Schaefer authored
Use readl_poll_timeout instead of explicit calculation Signed-off-by:
Thomas Schaefer <thomas.schaefer@kontron.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com>
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Thomas Schaefer authored
During QSPI reads, current is_controller_busy function sporadically fails with -ETIMEDOUT due to fixed number of 5 test loops. Using timer functions to wait 1000 us instead will fix this. Signed-off-by:
Thomas Schaefer <thomas.schaefer@kontron.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com>
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Heinrich Schuchardt authored
In void *rx_addr = NULL; rx_add = A; the first assignment has no effect. Remove it. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Rajat Srivastava authored
Some SoCs have different endianness of QSPI IP if compared to endianness of core. The function is_controller_busy() checks if the QSPI controller is busy or not, considering the endianness of the QSPI IP. Signed-off-by:
Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Frieder Schrempf authored
Part of upstream commit 48263504c8d501678acaa90c075f3f7cda17c316.
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Peng Fan authored
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size. The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly. Add the compatible entry for 6ul/7d. Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Suresh Gupta authored
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by:
Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by:
Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Suresh Gupta authored
It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by:
Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Alexander Stein authored
Pet the watchdog once upon each command call (qspi_xfer) and during each loop iteration in several commands. This fixes a watchdog reset especially during erase command. Signed-off-by:
Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Suresh Gupta authored
SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by:
Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Frieder Schrempf authored
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Denis Pynkin authored
PXE boot is broken with GCC 7.1 due option '-fstore-merging' enabled by default for '-O2': BOOTP broadcast 1 data abort pc : [<8ff8bb30>] lr : [<00004f1f>] reloc pc : [<17832b30>] lr : [<878abf1f>] sp : 8f558bc0 ip : 00000000 fp : 8ffef5a4 r10: 8ffed248 r9 : 8f558ee0 r8 : 8ffef594 r7 : 0000000e r6 : 8ffed700 r5 : 00000000 r4 : 8ffed74e r3 : 00060101 r2 : 8ffed230 r1 : 8ffed706 r0 : 00000ddd Flags: nzcv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Core reason is usage of structures for network headers without packed attribute. Reviewed-by:
Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by:
Denis Pynkin <denis.pynkin@collabora.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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- 21 Oct, 2019 1 commit
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Frieder Schrempf authored
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- 11 Apr, 2019 2 commits
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Frieder Schrempf authored
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Christophe Kerello authored
By checking ubifs source code, s_instances parameter is not used anymore. So, set this parameter and the associated source code under __UBOOT__ compilation. This also fixes a real bug, as with multiple mount operations, the update of the fs_supers linked list can cause memory corruption. Upstream commit: 5a08cfee3967 Signed-off-by:
Christophe Kerello <christophe.kerello@st.com> Signed-off-by:
Patrice Chotard <patrice.chotard@st.com>
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- 19 Dec, 2018 2 commits
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Fabio Estevam authored
Clear powerdown enable bit for WDOG3 on i.MX6ULL to avoid unwanted kernel reboots. Suggested-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Reviewed-by:
Stefano Babic <sbabic@denx.de>
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Fabio Estevam authored
i.MX6ULL has the same WDOG3 base address as i.MX6UL, so take this into account in the base address definition. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Reviewed-by:
Stefano Babic <sbabic@denx.de>
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- 18 Dec, 2018 4 commits
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Frieder Schrempf authored
Make it possible to use first, second and last page for bad block markers See merge request !1
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Frieder Schrempf authored
Some ESMT NANDs have been shipped by the manufacturer with bad block markers in first or last page, instead of first or second page. Also the datasheets for Cypress/Spansion/AMD NANDs claim that the first, second and last page needs to be checked. Therefore we need to scan all three of those pages to make sure to detect the markers correctly for these manufacturers. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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Frieder Schrempf authored
Add the manufacturer id of ESMT NANDs to apply manufacturer specific configuration. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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Frieder Schrempf authored
Currently supported bad block marker positions within the block are: * in first page only * in last page only * in first or second page Some ESMT NANDs have been shipped by the manufacturer with bad block markers in first or last page. Also the datasheets for Cypress/Spansion/AMD NANDs claim that the first, second and last page needs to be checked. Therefore we make it possible to set NAND_BBT_SCAN2NDPAGE and NAND_BBT_SCANLASTPAGE at the same time to scan/set all three pages. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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- 26 Jan, 2018 1 commit
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Eberhard Stoll authored
fix curl call
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- 15 Jan, 2018 2 commits
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Armin Mück authored
For proper authentication users must check the IVT before authenticating the kernel image. If the IVT DCD pointer is not 0, display an error as shown below and return a boot failure. Authenticate image from DDR location 0x12000000... Error: DCD pointer must be 0 Authenticate zImage Fail, Please check Backported to branch imx_v2015.04_4.1.15_1.0.0_ga. Signed-off-by:
Utkarsh Gupta <utkarsh.gupta@nxp.com> Signed-off-by:
Breno Lima <breno.lima@nxp.com>
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Armin Mück authored
For proper authentication users must check if the CSF is valid. This patch calls the csf_is_valid function prior to authenticating the image to parse the CSF and returns a failure if an invalid command is found as shown below. Authenticate image from DDR location 0x12000000... Check CSF for Write Data command before authenticating image Error - WRITE Data command found Authenticate zImage Fail, Please check Backported to branch imx_v2017.03_4.9.11_1.0.0_ga. Signed-off-by:
Utkarsh Gupta <utkarsh.gupta@nxp.com>
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- 22 Nov, 2017 1 commit
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Eberhard Stoll authored
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- 21 Nov, 2017 1 commit
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Maximilian Adducchio authored
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- 25 Oct, 2017 1 commit
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Frieder Schrempf authored
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- 19 Oct, 2017 1 commit
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Eberhard Stoll authored
Only part of the data was written to flash due to the lacking of program load (0x02) instruction
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- 10 Oct, 2017 1 commit
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Frieder Schrempf authored
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- 29 Sep, 2017 1 commit
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Maximilian Adducchio authored
set variable ethaddr only for first eth device. -> solves wrong address enumeration
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- 08 Sep, 2017 1 commit
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Exceet Yocto authored
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- 30 Aug, 2017 3 commits
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Exceet Yocto authored
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Exceet Yocto authored
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Exceet Yocto authored
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- 22 Aug, 2017 1 commit
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Frieder Schrempf authored
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