From 7a9d70231f0a01672b116700ffbd35fd2de60ced Mon Sep 17 00:00:00 2001
From: Gabriel Fernandez <gabriel.fernandez@st.com>
Date: Tue, 27 Oct 2020 14:09:32 +0100
Subject: [PATCH] stm32mp: use newly introduced minimal clock framework

Change call of:
stm32mp_clk_enable() / stm32mp_clk_disable() / stm32mp_clk_get_rate()
by
clk_enable() / clk_disable() / clk_get_rate()

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/182346
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>
---
 drivers/st/clk/stm32mp1_calib.c            |   5 +-
 drivers/st/clk/stm32mp1_clk.c              | 107 +++++++++++----------
 drivers/st/clk/stm32mp_clkfunc.c           |   3 +-
 drivers/st/crypto/stm32_hash.c             |  19 ++--
 drivers/st/ddr/stm32mp1_ddr.c              |   3 +-
 drivers/st/ddr/stm32mp1_ram.c              |   3 +-
 drivers/st/fmc/stm32_fmc2_nand.c           |   5 +-
 drivers/st/gpio/stm32_gpio.c               |   9 +-
 drivers/st/i2c/stm32_i2c.c                 |  21 ++--
 drivers/st/iwdg/stm32_iwdg.c               |  16 +--
 drivers/st/mmc/stm32_sdmmc2.c              |   5 +-
 drivers/st/rng/stm32_rng.c                 |   8 +-
 drivers/st/rtc/stm32_rtc.c                 |  21 ++--
 drivers/st/spi/stm32_qspi.c                |   5 +-
 drivers/st/tamper/stm32_tamp.c             |   3 +-
 drivers/st/timer/stm32_timer.c             |  19 ++--
 include/drivers/st/stm32mp1_clk.h          |   2 -
 plat/st/common/include/stm32mp_common.h    |   9 --
 plat/st/stm32mp1/bl2_plat_setup.c          |   7 +-
 plat/st/stm32mp1/plat_image_load.c         |   3 +-
 plat/st/stm32mp1/sp_min/sp_min_setup.c     |   5 +-
 plat/st/stm32mp1/stm32mp1_context.c        |  65 +++++++------
 plat/st/stm32mp1/stm32mp1_fconf_firewall.c |   6 +-
 plat/st/stm32mp1/stm32mp1_low_power.c      |   5 +-
 plat/st/stm32mp1/stm32mp1_pm.c             |   6 +-
 plat/st/stm32mp1/stm32mp1_private.c        |   3 +-
 plat/st/stm32mp1/stm32mp1_scmi.c           |  11 ++-
 plat/st/stm32mp1/stm32mp1_security.c       |   5 +-
 28 files changed, 197 insertions(+), 182 deletions(-)

diff --git a/drivers/st/clk/stm32mp1_calib.c b/drivers/st/clk/stm32mp1_calib.c
index 8a8993885..11a334303 100644
--- a/drivers/st/clk/stm32mp1_calib.c
+++ b/drivers/st/clk/stm32mp1_calib.c
@@ -17,6 +17,7 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/st/stm32_timer.h>
@@ -468,7 +469,7 @@ static void init_hsi_cal(void)
 		return;
 	}
 
-	stm32mp1_clk_cal_hsi.ref_freq = stm32mp_clk_get_rate(CK_HSI);
+	stm32mp1_clk_cal_hsi.ref_freq = clk_get_rate(CK_HSI);
 
 	/* Read initial value */
 	stm32mp1_clk_cal_hsi.cal_ref =
@@ -495,7 +496,7 @@ static void init_csi_cal(void)
 		return;
 	}
 
-	stm32mp1_clk_cal_csi.ref_freq = stm32mp_clk_get_rate(CK_CSI);
+	stm32mp1_clk_cal_csi.ref_freq = clk_get_rate(CK_CSI);
 
 	/* Read initial value */
 	stm32mp1_clk_cal_csi.cal_ref =
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index de94f389e..bb36b661f 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -18,6 +18,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_timer.h>
 #include <drivers/st/stm32mp_clkfunc.h>
@@ -1260,12 +1261,14 @@ static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt)
 	stm32mp1_clk_unlock(&refcount_lock);
 }
 
-void stm32mp_clk_enable(unsigned long id)
+static int stm32mp_clk_enable(unsigned long id)
 {
 	__stm32mp1_clk_enable(id, true);
+
+	return 0;
 }
 
-void stm32mp_clk_disable(unsigned long id)
+static void stm32mp_clk_disable(unsigned long id)
 {
 	__stm32mp1_clk_disable(id, true);
 }
@@ -1280,7 +1283,7 @@ void stm32mp1_clk_force_disable(unsigned long id)
 	__stm32mp1_clk_disable(id, false);
 }
 
-bool stm32mp_clk_is_enabled(unsigned long id)
+static bool stm32mp_clk_is_enabled(unsigned long id)
 {
 	int i;
 
@@ -1296,15 +1299,55 @@ bool stm32mp_clk_is_enabled(unsigned long id)
 	return __clk_is_enabled(gate_ref(i));
 }
 
-unsigned long stm32mp_clk_get_rate(unsigned long id)
+static unsigned long stm32mp_clk_get_rate(unsigned long id)
 {
+	uintptr_t rcc_base = stm32mp_rcc_base();
 	int p = stm32mp1_clk_get_parent(id);
+	uint32_t prescaler, timpre;
+	unsigned long parent_rate;
 
 	if (p < 0) {
 		return 0;
 	}
 
-	return get_clock_rate(p);
+	parent_rate = get_clock_rate(p);
+
+	switch (id) {
+	case TIM2_K:
+	case TIM3_K:
+	case TIM4_K:
+	case TIM5_K:
+	case TIM6_K:
+	case TIM7_K:
+	case TIM12_K:
+	case TIM13_K:
+	case TIM14_K:
+		prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
+			    RCC_APBXDIV_MASK;
+		timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
+			 RCC_TIMGXPRER_TIMGXPRE;
+		break;
+
+	case TIM1_K:
+	case TIM8_K:
+	case TIM15_K:
+	case TIM16_K:
+	case TIM17_K:
+		prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
+			    RCC_APBXDIV_MASK;
+		timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
+			 RCC_TIMGXPRER_TIMGXPRE;
+		break;
+
+	default:
+		return parent_rate;
+	}
+
+	if (prescaler == 0U) {
+		return parent_rate;
+	}
+
+	return parent_rate * (timpre + 1U) * 2U;
 }
 
 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
@@ -1816,50 +1859,6 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
 	}
 }
 
-unsigned long stm32mp_clk_timer_get_rate(unsigned long id)
-{
-	unsigned long parent_rate;
-	uint32_t prescaler, timpre;
-	uintptr_t rcc_base = stm32mp_rcc_base();
-
-	parent_rate = stm32mp_clk_get_rate(id);
-
-	switch (id) {
-	case TIM2_K:
-	case TIM3_K:
-	case TIM4_K:
-	case TIM5_K:
-	case TIM6_K:
-	case TIM7_K:
-	case TIM12_K:
-	case TIM13_K:
-	case TIM14_K:
-		prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
-			    RCC_APBXDIV_MASK;
-		timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
-			 RCC_TIMGXPRER_TIMGXPRE;
-		break;
-	case TIM1_K:
-	case TIM8_K:
-	case TIM15_K:
-	case TIM16_K:
-	case TIM17_K:
-		prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
-			    RCC_APBXDIV_MASK;
-		timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
-			 RCC_TIMGXPRER_TIMGXPRE;
-		break;
-	default:
-		return 0;
-	}
-
-	if (!prescaler) {
-		return parent_rate;
-	}
-
-	return parent_rate * (timpre + 1) * 2;
-}
-
 /*******************************************************************************
  * This function determines the number of needed RTC calendar read operations
  * to get consistent values (1 or 2 depending on clock frequencies).
@@ -3416,6 +3415,14 @@ static void sync_earlyboot_clocks_state(void)
 	}
 }
 
+static const clk_ops_t stm32mp_clk_ops = {
+	.enable		= stm32mp_clk_enable,
+	.disable	= stm32mp_clk_disable,
+	.is_enabled	= stm32mp_clk_is_enabled,
+	.get_rate	= stm32mp_clk_get_rate,
+	.get_parent	= stm32mp1_clk_get_parent,
+};
+
 int stm32mp1_clk_probe(void)
 {
 	unsigned long freq_khz;
@@ -3434,5 +3441,7 @@ int stm32mp1_clk_probe(void)
 
 	current_opp_khz = (uint32_t)freq_khz;
 
+	clk_register(&stm32mp_clk_ops);
+
 	return 0;
 }
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index 6bd4cae9a..6fbc27d63 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -12,6 +12,7 @@
 
 #include <arch_helpers.h>
 #include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32mp_clkfunc.h>
@@ -392,7 +393,7 @@ unsigned long fdt_get_uart_clock_freq(uintptr_t instance)
 		return 0UL;
 	}
 
-	return stm32mp_clk_get_rate((unsigned long)clk_id);
+	return clk_get_rate((unsigned long)clk_id);
 }
 
 /*******************************************************************************
diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c
index 317fd9eb8..9ee64a57e 100644
--- a/drivers/st/crypto/stm32_hash.c
+++ b/drivers/st/crypto/stm32_hash.c
@@ -14,6 +14,7 @@
 
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_hash.h>
 #include <drivers/st/stm32mp_reset.h>
@@ -189,7 +190,7 @@ int stm32_hash_update(const uint8_t *buffer, size_t length)
 		return 0;
 	}
 
-	stm32mp_clk_enable(stm32_hash.clock);
+	clk_enable(stm32_hash.clock);
 
 	if (stm32_remain.length != 0U) {
 		uint32_t copysize;
@@ -231,7 +232,7 @@ int stm32_hash_update(const uint8_t *buffer, size_t length)
 	}
 
 exit:
-	stm32mp_clk_disable(stm32_hash.clock);
+	clk_disable(stm32_hash.clock);
 
 	return ret;
 }
@@ -240,12 +241,12 @@ int stm32_hash_final(uint8_t *digest)
 {
 	int ret;
 
-	stm32mp_clk_enable(stm32_hash.clock);
+	clk_enable(stm32_hash.clock);
 
 	if (stm32_remain.length != 0U) {
 		ret = hash_write_data(stm32_remain.buffer);
 		if (ret != 0) {
-			stm32mp_clk_disable(stm32_hash.clock);
+			clk_disable(stm32_hash.clock);
 			return ret;
 		}
 
@@ -260,7 +261,7 @@ int stm32_hash_final(uint8_t *digest)
 
 	ret = hash_get_digest(digest);
 
-	stm32mp_clk_disable(stm32_hash.clock);
+	clk_disable(stm32_hash.clock);
 
 	return ret;
 }
@@ -280,11 +281,11 @@ int stm32_hash_final_update(const uint8_t *buffer, uint32_t length,
 
 void stm32_hash_init(enum stm32_hash_algo_mode mode)
 {
-	stm32mp_clk_enable(stm32_hash.clock);
+	clk_enable(stm32_hash.clock);
 
 	hash_hw_init(mode);
 
-	stm32mp_clk_disable(stm32_hash.clock);
+	clk_disable(stm32_hash.clock);
 
 	zeromem(&stm32_remain, sizeof(stm32_remain));
 }
@@ -321,7 +322,7 @@ int stm32_hash_register(void)
 	stm32_hash.base = hash_info.base;
 	stm32_hash.clock = hash_info.clock;
 
-	stm32mp_clk_enable(stm32_hash.clock);
+	clk_enable(stm32_hash.clock);
 
 	if (hash_info.reset >= 0) {
 		uint32_t id = (uint32_t)hash_info.reset;
@@ -335,7 +336,7 @@ int stm32_hash_register(void)
 		}
 	}
 
-	stm32mp_clk_disable(stm32_hash.clock);
+	clk_disable(stm32_hash.clock);
 
 	return 0;
 }
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index 2fcbbd967..84ed968d7 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -12,6 +12,7 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32mp_pmic.h>
 #include <drivers/st/stm32mp1_ddr.h>
@@ -615,7 +616,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
 	 */
 
 	/* Change Bypass Mode Frequency Range */
-	if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
+	if (clk_get_rate(DDRPHYC) < 100000000U) {
 		mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
 				DDRPHYC_DLLGCR_BPS200);
 	} else {
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c
index ab18fd934..3918eb7be 100644
--- a/drivers/st/ddr/stm32mp1_ram.c
+++ b/drivers/st/ddr/stm32mp1_ram.c
@@ -13,6 +13,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
 #include <drivers/st/stm32mp1_ddr.h>
 #include <drivers/st/stm32mp1_ddr_helpers.h>
 #include <drivers/st/stm32mp1_ram.h>
@@ -30,7 +31,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
 
 	ddr_enable_clock();
 
-	ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC);
+	ddrphy_clk = clk_get_rate(DDRPHYC);
 
 	VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
 		mem_speed, ddrphy_clk / 1000U);
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
index a58a243ad..503e25987 100644
--- a/drivers/st/fmc/stm32_fmc2_nand.c
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -14,6 +14,7 @@
 #include <platform_def.h>
 
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/raw_nand.h>
 #include <drivers/st/stm32_fmc2_nand.h>
@@ -162,7 +163,7 @@ static uintptr_t fmc2_base(void)
 static void stm32_fmc2_nand_setup_timing(void)
 {
 	struct stm32_fmc2_nand_timings tims;
-	unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id);
+	unsigned long hclk = clk_get_rate(stm32_fmc2.clock_id);
 	unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U);
 	unsigned long timing, tar, tclr, thiz, twait;
 	unsigned long tset_mem, tset_att, thold_mem, thold_att;
@@ -918,7 +919,7 @@ int stm32_fmc2_init(void)
 	}
 
 	/* Enable Clock */
-	stm32mp_clk_enable(stm32_fmc2.clock_id);
+	clk_enable(stm32_fmc2.clock_id);
 
 	/* Reset IP */
 	ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 7d63262d7..75707e63a 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -14,6 +14,7 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32mp_clkfunc.h>
 #include <lib/mmio.h>
@@ -208,7 +209,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp_clk_enable(clock);
+	clk_enable(clock);
 
 	mmio_clrbits_32(base + GPIO_MODE_OFFSET,
 			((uint32_t)GPIO_MODE_MASK << (pin << 1)));
@@ -254,7 +255,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
 	VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
 		mmio_read_32(base + GPIO_AFRH_OFFSET));
 
-	stm32mp_clk_disable(clock);
+	clk_disable(clock);
 
 	if (status == DT_SECURE) {
 		stm32mp_register_secure_gpio(bank, pin);
@@ -273,7 +274,7 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp_clk_enable(clock);
+	clk_enable(clock);
 
 	if (secure) {
 		mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
@@ -281,5 +282,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 		mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
 	}
 
-	stm32mp_clk_disable(clock);
+	clk_disable(clock);
 }
diff --git a/drivers/st/i2c/stm32_i2c.c b/drivers/st/i2c/stm32_i2c.c
index 860998d8f..3e4b96a2c 100644
--- a/drivers/st/i2c/stm32_i2c.c
+++ b/drivers/st/i2c/stm32_i2c.c
@@ -15,6 +15,7 @@
 
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32_i2c.h>
@@ -373,7 +374,7 @@ static int i2c_setup_timing(struct i2c_handle_s *hi2c,
 	int rc = 0;
 	uint32_t clock_src;
 
-	clock_src = (uint32_t)stm32mp_clk_get_rate(hi2c->clock);
+	clock_src = (uint32_t)clk_get_rate(hi2c->clock);
 	if (clock_src == 0U) {
 		ERROR("I2C clock rate is 0\n");
 		return -EINVAL;
@@ -522,7 +523,7 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c,
 		return rc;
 	}
 
-	stm32mp_clk_enable(hi2c->clock);
+	clk_enable(hi2c->clock);
 
 	/* Disable the selected I2C peripheral */
 	mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
@@ -584,11 +585,11 @@ int stm32_i2c_init(struct i2c_handle_s *hi2c,
 						I2C_ANALOGFILTER_DISABLE);
 	if (rc != 0) {
 		ERROR("Cannot initialize I2C analog filter (%d)\n", rc);
-		stm32mp_clk_disable(hi2c->clock);
+		clk_disable(hi2c->clock);
 		return rc;
 	}
 
-	stm32mp_clk_disable(hi2c->clock);
+	clk_disable(hi2c->clock);
 
 	return rc;
 }
@@ -912,7 +913,7 @@ static int i2c_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
 		return -EINVAL;
 	}
 
-	stm32mp_clk_enable(hi2c->clock);
+	clk_enable(hi2c->clock);
 
 	hi2c->lock = 1;
 
@@ -1012,7 +1013,7 @@ static int i2c_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
 
 bail:
 	hi2c->lock = 0;
-	stm32mp_clk_disable(hi2c->clock);
+	clk_disable(hi2c->clock);
 
 	return rc;
 }
@@ -1093,7 +1094,7 @@ static int i2c_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
 		return  -EINVAL;
 	}
 
-	stm32mp_clk_enable(hi2c->clock);
+	clk_enable(hi2c->clock);
 
 	hi2c->lock = 1;
 
@@ -1181,7 +1182,7 @@ static int i2c_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
 
 bail:
 	hi2c->lock = 0;
-	stm32mp_clk_disable(hi2c->clock);
+	clk_disable(hi2c->clock);
 
 	return rc;
 }
@@ -1246,7 +1247,7 @@ bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
 		return rc;
 	}
 
-	stm32mp_clk_enable(hi2c->clock);
+	clk_enable(hi2c->clock);
 
 	hi2c->lock = 1;
 	hi2c->i2c_mode = I2C_MODE_NONE;
@@ -1338,7 +1339,7 @@ bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
 
 bail:
 	hi2c->lock = 0;
-	stm32mp_clk_disable(hi2c->clock);
+	clk_disable(hi2c->clock);
 
 	return rc;
 }
diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
index ee7c8c6f1..1808ca741 100644
--- a/drivers/st/iwdg/stm32_iwdg.c
+++ b/drivers/st/iwdg/stm32_iwdg.c
@@ -15,6 +15,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/arm/gicv2.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_iwdg.h>
 #include <drivers/st/stm32mp_clkfunc.h>
@@ -94,11 +95,11 @@ void __dead2 stm32_iwdg_it_handler(int id)
 
 	stm32_iwdg_refresh();
 
-	stm32mp_clk_enable(iwdg->clock);
+	clk_enable(iwdg->clock);
 
 	mmio_setbits_32(iwdg->base + IWDG_EWCR_OFFSET, IWDG_EWCR_EWIC);
 
-	stm32mp_clk_disable(iwdg->clock);
+	clk_disable(iwdg->clock);
 
 	/* Ack interrupt as we do not return from next call */
 	gicv2_end_of_interrupt(id);
@@ -145,11 +146,10 @@ static int stm32_iwdg_conf_etimeout(int node, struct stm32_iwdg_instance *iwdg)
 	}
 
 	/* Prescaler fix to 256 */
-	reload_ll = (unsigned long long)dt_secure_timeout *
-		   stm32mp_clk_get_rate(id_lsi);
+	reload_ll = (unsigned long long)dt_secure_timeout * clk_get_rate(id_lsi);
 	reload = ((uint32_t)(reload_ll >> 8) - 1U) & IWDG_EWCR_EWIT_MASK;
 
-	stm32mp_clk_enable(iwdg->clock);
+	clk_enable(iwdg->clock);
 
 	mmio_write_32(iwdg->base + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
 	mmio_write_32(iwdg->base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
@@ -168,7 +168,7 @@ static int stm32_iwdg_conf_etimeout(int node, struct stm32_iwdg_instance *iwdg)
 		panic();
 	}
 
-	stm32mp_clk_disable(iwdg->clock);
+	clk_disable(iwdg->clock);
 
 	return (timeout == 0U) ? -ETIMEDOUT : 0;
 }
@@ -183,12 +183,12 @@ void stm32_iwdg_refresh(void)
 
 		/* 0x00000000 is not a valid address for IWDG peripherals */
 		if (iwdg->base != 0U) {
-			stm32mp_clk_enable(iwdg->clock);
+			clk_enable(iwdg->clock);
 
 			mmio_write_32(iwdg->base + IWDG_KR_OFFSET,
 				      IWDG_KR_RELOAD_KEY);
 
-			stm32mp_clk_disable(iwdg->clock);
+			clk_disable(iwdg->clock);
 		}
 	}
 }
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index d43a87dd9..8c203a4c0 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -15,6 +15,7 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/mmc.h>
 #include <drivers/st/stm32_gpio.h>
@@ -789,7 +790,7 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
 		return -ENOMEM;
 	}
 
-	stm32mp_clk_enable(sdmmc2_params.clock_id);
+	clk_enable(sdmmc2_params.clock_id);
 
 	rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
 	if (rc != 0) {
@@ -802,7 +803,7 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
 	}
 	mdelay(1);
 
-	sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
+	sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id);
 	sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
 
 	return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
diff --git a/drivers/st/rng/stm32_rng.c b/drivers/st/rng/stm32_rng.c
index dfe4597fb..461d50c81 100644
--- a/drivers/st/rng/stm32_rng.c
+++ b/drivers/st/rng/stm32_rng.c
@@ -13,6 +13,7 @@
 #include <platform_def.h>
 
 #include <arch_helpers.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_rng.h>
 #include <drivers/st/stm32mp_reset.h>
@@ -64,7 +65,7 @@ int stm32_rng_read(uint8_t *out, uint32_t size)
 		return -EPERM;
 	}
 
-	stm32mp_clk_enable(stm32_rng.clock);
+	clk_enable(stm32_rng.clock);
 
 	if ((mmio_read_32(stm32_rng.base + RNG_CR) & RNG_CR_RNGEN) == 0U) {
 		mmio_write_32(stm32_rng.base + RNG_CR,
@@ -121,7 +122,7 @@ int stm32_rng_read(uint8_t *out, uint32_t size)
 	}
 
 bail:
-	stm32mp_clk_disable(stm32_rng.clock);
+	clk_disable(stm32_rng.clock);
 
 	if (rc != 0) {
 		memset(out, 0, buf - out);
@@ -168,9 +169,6 @@ int stm32_rng_init(void)
 	}
 	stm32_rng.clock = (unsigned long)dt_rng.clock;
 
-	stm32mp_clk_enable(stm32_rng.clock);
-	stm32mp_clk_disable(stm32_rng.clock);
-
 	if (dt_rng.reset >= 0) {
 		int ret;
 
diff --git a/drivers/st/rtc/stm32_rtc.c b/drivers/st/rtc/stm32_rtc.c
index 3bfaed772..58d599b17 100644
--- a/drivers/st/rtc/stm32_rtc.c
+++ b/drivers/st/rtc/stm32_rtc.c
@@ -10,6 +10,7 @@
 
 #include <arch_helpers.h>
 #include <common/debug.h>
+#include <drivers/clk.h>
 #include <drivers/st/stm32_rtc.h>
 #include <drivers/st/stm32mp_clkfunc.h>
 #include <lib/mmio.h>
@@ -211,7 +212,7 @@ void stm32_rtc_get_calendar(struct stm32_rtc_calendar *calendar)
 	bool read_twice = stm32mp1_rtc_get_read_twice();
 
 	stm32_rtc_regs_lock();
-	stm32mp_clk_enable(rtc_dev.clock);
+	clk_enable(rtc_dev.clock);
 
 	stm32_rtc_read_calendar(calendar);
 
@@ -225,7 +226,7 @@ void stm32_rtc_get_calendar(struct stm32_rtc_calendar *calendar)
 		}
 	}
 
-	stm32mp_clk_disable(rtc_dev.clock);
+	clk_disable(rtc_dev.clock);
 	stm32_rtc_regs_unlock();
 }
 
@@ -379,7 +380,7 @@ unsigned long long stm32_rtc_diff_calendar(struct stm32_rtc_calendar *cur,
 	struct stm32_rtc_time curr_t;
 	struct stm32_rtc_time ref_t;
 
-	stm32mp_clk_enable(rtc_dev.clock);
+	clk_enable(rtc_dev.clock);
 
 	stm32_rtc_get_date(cur, &curr_t);
 	stm32_rtc_get_date(ref, &ref_t);
@@ -390,7 +391,7 @@ unsigned long long stm32_rtc_diff_calendar(struct stm32_rtc_calendar *cur,
 	diff_in_ms += stm32_rtc_diff_time(&curr_t, &ref_t);
 	diff_in_ms += stm32_rtc_diff_date(&curr_t, &ref_t);
 
-	stm32mp_clk_disable(rtc_dev.clock);
+	clk_disable(rtc_dev.clock);
 
 	return (unsigned long long)diff_in_ms;
 }
@@ -401,7 +402,7 @@ unsigned long long stm32_rtc_diff_calendar(struct stm32_rtc_calendar *cur,
 void stm32_rtc_get_timestamp(struct stm32_rtc_time *tamp_ts)
 {
 	stm32_rtc_regs_lock();
-	stm32mp_clk_enable(rtc_dev.clock);
+	clk_enable(rtc_dev.clock);
 
 	if ((mmio_read_32(rtc_dev.base + RTC_SR) & RTC_SR_TSF) != 0U) {
 		/* Print timestamp for tamper event */
@@ -414,7 +415,7 @@ void stm32_rtc_get_timestamp(struct stm32_rtc_time *tamp_ts)
 		}
 	}
 
-	stm32mp_clk_disable(rtc_dev.clock);
+	clk_disable(rtc_dev.clock);
 	stm32_rtc_regs_unlock();
 }
 
@@ -425,7 +426,7 @@ void stm32_rtc_get_timestamp(struct stm32_rtc_time *tamp_ts)
 void stm32_rtc_set_tamper_timestamp(void)
 {
 	stm32_rtc_regs_lock();
-	stm32mp_clk_enable(rtc_dev.clock);
+	clk_enable(rtc_dev.clock);
 
 	stm32_rtc_write_unprotect();
 
@@ -437,7 +438,7 @@ void stm32_rtc_set_tamper_timestamp(void)
 
 	stm32_rtc_write_protect();
 
-	stm32mp_clk_disable(rtc_dev.clock);
+	clk_disable(rtc_dev.clock);
 	stm32_rtc_regs_unlock();
 }
 
@@ -448,11 +449,11 @@ bool stm32_rtc_is_timestamp_enable(void)
 {
 	bool ret;
 
-	stm32mp_clk_enable(rtc_dev.clock);
+	clk_enable(rtc_dev.clock);
 
 	ret = (mmio_read_32(rtc_dev.base + RTC_CR) & RTC_CR_TAMPTS) != 0U;
 
-	stm32mp_clk_disable(rtc_dev.clock);
+	clk_disable(rtc_dev.clock);
 
 	return ret;
 }
diff --git a/drivers/st/spi/stm32_qspi.c b/drivers/st/spi/stm32_qspi.c
index d67f8313f..966716d68 100644
--- a/drivers/st/spi/stm32_qspi.c
+++ b/drivers/st/spi/stm32_qspi.c
@@ -10,6 +10,7 @@
 
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/spi_mem.h>
 #include <drivers/st/stm32_gpio.h>
@@ -363,7 +364,7 @@ static void stm32_qspi_release_bus(void)
 
 static int stm32_qspi_set_speed(unsigned int hz)
 {
-	unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id);
+	unsigned long qspi_clk = clk_get_rate(stm32_qspi.clock_id);
 	uint32_t prescaler = UINT8_MAX;
 	uint32_t csht;
 	int ret;
@@ -493,7 +494,7 @@ int stm32_qspi_init(void)
 	stm32_qspi.clock_id = (unsigned long)info.clock;
 	stm32_qspi.reset_id = (unsigned int)info.reset;
 
-	stm32mp_clk_enable(stm32_qspi.clock_id);
+	clk_enable(stm32_qspi.clock_id);
 
 	ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS);
 	if (ret != 0) {
diff --git a/drivers/st/tamper/stm32_tamp.c b/drivers/st/tamper/stm32_tamp.c
index 47f2d4046..c9a9e9aef 100644
--- a/drivers/st/tamper/stm32_tamp.c
+++ b/drivers/st/tamper/stm32_tamp.c
@@ -11,6 +11,7 @@
 
 #include <platform_def.h>
 
+#include <drivers/clk.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32_rng.h>
 #include <drivers/st/stm32_rtc.h>
@@ -334,7 +335,7 @@ int stm32_tamp_init(void)
 	stm32_tamp.clock = (uint32_t)dt_tamp.clock;
 
 	/* Init Tamp clock */
-	stm32mp_clk_enable(stm32_tamp.clock);
+	clk_enable(stm32_tamp.clock);
 
 	/* Reset Tamp register without modifying backup registers conf */
 	stm32_tamp_reset_register(stm32_tamp.base);
diff --git a/drivers/st/timer/stm32_timer.c b/drivers/st/timer/stm32_timer.c
index 34f1f6206..1899707f7 100644
--- a/drivers/st/timer/stm32_timer.c
+++ b/drivers/st/timer/stm32_timer.c
@@ -12,6 +12,7 @@
 
 #include <platform_def.h>
 
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_timer.h>
 #include <lib/mmio.h>
@@ -90,13 +91,13 @@ static int stm32_timer_get_dt_node(struct dt_node_info *info, int offset)
 
 static int stm32_timer_config(struct stm32_timer_instance *timer)
 {
-	stm32mp_clk_enable(timer->clk);
+	clk_enable(timer->clk);
 
-	timer->freq = stm32mp_clk_timer_get_rate(timer->clk);
+	timer->freq = clk_get_rate(timer->clk);
 
 	if (timer->freq < TIM_MIN_FREQ_CALIB) {
 		WARN("Timer is not accurate enough for calibration\n");
-		stm32mp_clk_disable(timer->clk);
+		clk_disable(timer->clk);
 		return -EINVAL;
 	}
 
@@ -119,7 +120,7 @@ static int stm32_timer_config(struct stm32_timer_instance *timer)
 		mmio_setbits_32(timer->base + TIM_CCER, TIM_CCER_CC1E);
 	}
 
-	stm32mp_clk_disable(timer->clk);
+	clk_disable(timer->clk);
 
 	return 0;
 }
@@ -135,7 +136,7 @@ static uint32_t stm32_timer_start_capture(struct stm32_timer_instance *timer)
 		return 0U;
 	}
 
-	stm32mp_clk_enable(timer->clk);
+	clk_enable(timer->clk);
 
 	mmio_write_32(timer->base + TIM_SR, 0U);
 	while (((mmio_read_32(timer->base + TIM_SR) &
@@ -175,7 +176,7 @@ static uint32_t stm32_timer_start_capture(struct stm32_timer_instance *timer)
 		 TIM_THRESHOLD);
 
 out:
-	stm32mp_clk_disable(timer->clk);
+	clk_disable(timer->clk);
 
 	if (timeout == 0U) {
 		return 0U;
@@ -285,8 +286,7 @@ int stm32_timer_init(void)
 				timer = &stm32_timer[HSI_CAL];
 				timer->base = dt_timer.base;
 				timer->clk = dt_timer.clock;
-				timer->freq =
-					stm32mp_clk_timer_get_rate(timer->clk);
+				timer->freq = clk_get_rate(timer->clk);
 				timer->cal_input =
 					(uint8_t)fdt32_to_cpu(*cuint);
 				if (stm32_timer_config(timer) < 0) {
@@ -301,8 +301,7 @@ int stm32_timer_init(void)
 				timer = &stm32_timer[CSI_CAL];
 				timer->base = dt_timer.base;
 				timer->clk = dt_timer.clock;
-				timer->freq =
-					stm32mp_clk_timer_get_rate(timer->clk);
+				timer->freq = clk_get_rate(timer->clk);
 				timer->cal_input =
 					(uint8_t)fdt32_to_cpu(*cuint);
 				if (stm32_timer_config(timer) < 0) {
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h
index 802a4c65b..70894413d 100644
--- a/include/drivers/st/stm32mp1_clk.h
+++ b/include/drivers/st/stm32mp1_clk.h
@@ -39,8 +39,6 @@ bool stm32mp1_rcc_is_mckprot(void);
 void stm32mp1_clk_force_enable(unsigned long id);
 void stm32mp1_clk_force_disable(unsigned long id);
 
-unsigned long stm32mp_clk_timer_get_rate(unsigned long id);
-
 bool stm32mp1_rtc_get_read_twice(void);
 
 /* SMP protection on RCC registers access */
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index c3da20983..819fc9cd1 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -106,15 +106,6 @@ void stm32mp_print_boardinfo(void);
 /* Check HW CPU OPP support */
 bool stm32mp_supports_cpu_opp(uint32_t opp_id);
 
-/*
- * Util for clock gating and to get clock rate for stm32 and platform drivers
- * @id: Target clock ID, ID used in clock DT bindings
- */
-bool stm32mp_clk_is_enabled(unsigned long id);
-void stm32mp_clk_enable(unsigned long id);
-void stm32mp_clk_disable(unsigned long id);
-unsigned long stm32mp_clk_get_rate(unsigned long id);
-
 /* Initialise the IO layer and register platform IO devices */
 void stm32mp_io_setup(void);
 
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index ca88bd4d0..aa8852f56 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -14,6 +14,7 @@
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <common/desc_image_load.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/st/bsec.h>
@@ -466,11 +467,11 @@ void bl2_el3_plat_arch_setup(void)
 		panic();
 	}
 
-	stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
+	clk_enable((unsigned long)dt_uart_info.clock);
 
 	reset_uart((uint32_t)dt_uart_info.reset);
 
-	clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
+	clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
 
 	if (console_stm32_register(dt_uart_info.base, clk_rate,
 				   STM32MP_UART_BAUDRATE, &console) == 0) {
@@ -690,7 +691,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
 			if (wakeup_ddr_sr) {
 				bl_mem_params->ep_info.pc = stm32_pm_get_optee_ep();
 				if (stm32mp1_addr_inside_backupsram(bl_mem_params->ep_info.pc)) {
-					stm32mp_clk_enable(BKPSRAM);
+					clk_enable(BKPSRAM);
 				}
 
 				break;
diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c
index 8a56ac880..c6a30de5b 100644
--- a/plat/st/stm32mp1/plat_image_load.c
+++ b/plat/st/stm32mp1/plat_image_load.c
@@ -8,6 +8,7 @@
 
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
+#include <drivers/clk.h>
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
 
@@ -45,7 +46,7 @@ bl_load_info_t *plat_get_bl_image_load_info(void)
 		bl32->ep_info.pc = stm32_pm_get_optee_ep();
 
 		if (stm32mp1_addr_inside_backupsram(bl32->ep_info.pc)) {
-			stm32mp_clk_enable(BKPSRAM);
+			clk_enable(BKPSRAM);
 		}
 #else
 		/* Set ep_info PC to 0, to inform BL32 it is a reset after STANDBY */
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index d8d9f45fe..00b93c3ee 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -16,6 +16,7 @@
 #include <context.h>
 #include <drivers/arm/gicv2.h>
 #include <drivers/arm/tzc400.h>
+#include <drivers/clk.h>
 #include <drivers/generic_delay_timer.h>
 #include <drivers/st/bsec.h>
 #include <drivers/st/etzpc.h>
@@ -209,12 +210,12 @@ static uintptr_t get_saved_pc(void)
 		tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
 	uint32_t magic_nb;
 
-	stm32mp_clk_enable(RTCAPB);
+	clk_enable(RTCAPB);
 
 	magic_nb = mmio_read_32(bkpr_core1_magic);
 	saved_pc = mmio_read_32(bkpr_core1_addr);
 
-	stm32mp_clk_disable(RTCAPB);
+	clk_disable(RTCAPB);
 
 	if (magic_nb != BOOT_API_A7_CORE0_MAGIC_NUMBER) {
 		return 0U;
diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c
index 29a24b15e..fd0f08fd7 100644
--- a/plat/st/stm32mp1/stm32mp1_context.c
+++ b/plat/st/stm32mp1/stm32mp1_context.c
@@ -12,6 +12,7 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <context.h>
+#include <drivers/clk.h>
 #include <drivers/st/stm32_rtc.h>
 #include <drivers/st/stm32mp_clkfunc.h>
 #include <drivers/st/stm32mp1_ddr_regs.h>
@@ -113,7 +114,7 @@ uint32_t stm32_pm_get_optee_ep(void)
 	struct backup_data_s *backup_data;
 	uint32_t ep;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	/* Context & Data to be saved at the beginning of Backup SRAM */
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
@@ -133,14 +134,14 @@ uint32_t stm32_pm_get_optee_ep(void)
 
 	ep = backup_data->core0_resume_hint;
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	return ep;
 }
 
 void stm32_clean_context(void)
 {
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 #if defined(IMAGE_BL2)
 	zeromem((void *)STM32MP_BACKUP_RAM_BASE, sizeof(struct backup_data_s));
@@ -148,7 +149,7 @@ void stm32_clean_context(void)
 	zeromem((void *)get_bl32_backup_data(), sizeof(struct backup_bl32_data_s));
 #endif
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
 
 #if defined(IMAGE_BL32)
@@ -160,11 +161,11 @@ void stm32mp1_pm_save_clock_cfg(size_t offset, uint8_t *data, size_t size)
 		panic();
 	}
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	memcpy(backup_data->clock_cfg + offset, data, size);
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
 
 void stm32mp1_pm_restore_clock_cfg(size_t offset, uint8_t *data, size_t size)
@@ -174,11 +175,11 @@ void stm32mp1_pm_restore_clock_cfg(size_t offset, uint8_t *data, size_t size)
 	if (offset + size > sizeof(backup_data->clock_cfg))
 		panic();
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	memcpy(data, backup_data->clock_cfg + offset, size);
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
 
 int stm32_save_context(uint32_t zq0cr0_zdata,
@@ -192,7 +193,7 @@ int stm32_save_context(uint32_t zq0cr0_zdata,
 
 	stm32mp1_clock_suspend();
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	/* Context & Data to be saved at the beginning of Backup SRAM */
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
@@ -230,7 +231,7 @@ int stm32_save_context(uint32_t zq0cr0_zdata,
 
 	save_clock_pm_context();
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	return 0;
 }
@@ -247,7 +248,7 @@ int stm32_restore_context(void)
 	/* Context & Data to be saved at the beginning of Backup SRAM */
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	stm32mp1_clk_lp_load_opp_pll1_settings(backup_data->pll1_settings,
 					       sizeof(backup_data->pll1_settings));
@@ -282,7 +283,7 @@ int stm32_restore_context(void)
 						   &backup_bl32_data->rtc);
 	stm32mp_stgen_restore_counter(backup_bl32_data->stgen, stdby_time_in_ms);
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	stm32mp1_clock_resume();
 
@@ -294,13 +295,13 @@ unsigned long long stm32_get_stgen_from_context(void)
 	struct backup_bl32_data_s *backup_data;
 	unsigned long long stgen_cnt;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = get_bl32_backup_data();
 
 	stgen_cnt = backup_data->stgen;
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	return stgen_cnt;
 }
@@ -311,7 +312,7 @@ void stm32_context_get_bl2_low_power_params(uintptr_t *bl2_code_base,
 {
 	struct backup_data_s *backup_data;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
@@ -326,7 +327,7 @@ void stm32_context_get_bl2_low_power_params(uintptr_t *bl2_code_base,
 	*bl2_code_end = (uintptr_t)backup_data->bl2_code_end;
 	*bl2_end = (uintptr_t)backup_data->bl2_end;
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
 
 #endif /* IMAGE_BL32 */
@@ -336,7 +337,7 @@ void stm32_context_save_bl2_param(void)
 {
 	struct backup_data_s *backup_data;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
@@ -346,7 +347,7 @@ void stm32_context_save_bl2_param(void)
 	backup_data->bl2_end = BL2_END;
 	backup_data->magic = MAILBOX_MAGIC_V3;
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
 #endif
 
@@ -355,14 +356,14 @@ uint32_t stm32_get_zdata_from_context(void)
 	struct backup_data_s *backup_data;
 	uint32_t zdata;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
 	zdata = (backup_data->zq0cr0_zdata >> DDRPHYC_ZQ0CRN_ZDATA_SHIFT) &
 		DDRPHYC_ZQ0CRN_ZDATA_MASK;
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	return zdata;
 }
@@ -389,7 +390,7 @@ int stm32_get_pll1_settings_from_context(void)
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	ret = pll1_settings_in_context(backup_data);
 	if (ret == 0) {
@@ -399,7 +400,7 @@ int stm32_get_pll1_settings_from_context(void)
 		stm32mp1_clk_lp_load_opp_pll1_settings(data, size);
 	}
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	return ret;
 }
@@ -410,14 +411,14 @@ bool stm32_are_pll1_settings_valid_in_context(void)
 	uint32_t *data;
 	bool is_valid;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 	data = (uint32_t *)backup_data->pll1_settings;
 
 	is_valid = (data[0] == PLL1_SETTINGS_VALID_ID);
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 
 	return is_valid;
 }
@@ -426,14 +427,14 @@ int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
 {
 	uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
 
-	stm32mp_clk_enable(RTCAPB);
+	clk_enable(RTCAPB);
 
 	mmio_clrsetbits_32(bkpr_itf_idx,
 			   TAMP_BOOT_ITF_MASK,
 			   ((interface << 4) | (instance & 0xFU)) <<
 			   TAMP_BOOT_ITF_SHIFT);
 
-	stm32mp_clk_disable(RTCAPB);
+	clk_disable(RTCAPB);
 
 	return 0;
 }
@@ -443,11 +444,11 @@ int stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
 	uint32_t itf;
 	uint32_t bkpr = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
 
-	stm32mp_clk_enable(RTCAPB);
+	clk_enable(RTCAPB);
 
 	itf = (mmio_read_32(bkpr) & TAMP_BOOT_ITF_MASK) >> TAMP_BOOT_ITF_SHIFT;
 
-	stm32mp_clk_disable(RTCAPB);
+	clk_disable(RTCAPB);
 
 	*interface = itf >> 4;
 	*instance = itf & 0xFU;
@@ -466,7 +467,7 @@ void stm32_save_ddr_training_area(void)
 	struct backup_data_s *backup_data;
 	int ret __unused;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
@@ -482,7 +483,7 @@ void stm32_save_ddr_training_area(void)
 	ret = mmap_remove_dynamic_region(STM32MP_DDR_BASE, PAGE_SIZE);
 	assert(ret == 0);
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
 #endif
 
@@ -490,7 +491,7 @@ void stm32_restore_ddr_training_area(void)
 {
 	struct backup_data_s *backup_data;
 
-	stm32mp_clk_enable(BKPSRAM);
+	clk_enable(BKPSRAM);
 
 	backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
 
@@ -499,5 +500,5 @@ void stm32_restore_ddr_training_area(void)
 	       TRAINING_AREA_SIZE);
 	dsb();
 
-	stm32mp_clk_disable(BKPSRAM);
+	clk_disable(BKPSRAM);
 }
diff --git a/plat/st/stm32mp1/stm32mp1_fconf_firewall.c b/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
index f2699e376..16aee904e 100644
--- a/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
+++ b/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
@@ -11,7 +11,7 @@
 #include <common/debug.h>
 #include <common/fdt_wrappers.h>
 #include <drivers/arm/tzc400.h>
-#include <drivers/st/stm32mp1_clk.h>
+#include <drivers/clk.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/fconf/fconf.h>
 #include <lib/object_pool.h>
@@ -32,8 +32,8 @@ struct dt_id_attr {
 
 void stm32mp1_arch_security_setup(void)
 {
-	stm32mp_clk_enable(TZC1);
-	stm32mp_clk_enable(TZC2);
+	clk_enable(TZC1);
+	clk_enable(TZC2);
 
 	tzc400_init(STM32MP1_TZC_BASE);
 	tzc400_disable_filters();
diff --git a/plat/st/stm32mp1/stm32mp1_low_power.c b/plat/st/stm32mp1/stm32mp1_low_power.c
index 806df348f..48ac9bddf 100644
--- a/plat/st/stm32mp1/stm32mp1_low_power.c
+++ b/plat/st/stm32mp1/stm32mp1_low_power.c
@@ -11,6 +11,7 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/arm/gicv2.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32_iwdg.h>
 #include <drivers/st/stm32_rtc.h>
@@ -192,7 +193,7 @@ static void enter_cstop(uint32_t mode, uint32_t nsec_addr)
 
 	zq0cr0_zdata = ddr_get_io_calibration_val();
 
-	stm32mp_clk_enable(RTCAPB);
+	clk_enable(RTCAPB);
 
 	mmio_write_32(bkpr_core1_addr, 0);
 	mmio_write_32(bkpr_core1_magic, 0);
@@ -232,7 +233,7 @@ static void enter_cstop(uint32_t mode, uint32_t nsec_addr)
 		}
 	}
 
-	stm32mp_clk_disable(RTCAPB);
+	clk_disable(RTCAPB);
 
 	enter_cstop_done = true;
 }
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index a20a3d3a9..957929f71 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -14,8 +14,8 @@
 #include <common/debug.h>
 #include <drivers/arm/gic_common.h>
 #include <drivers/arm/gicv2.h>
+#include <drivers/clk.h>
 #include <drivers/delay_timer.h>
-#include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_rcc.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
@@ -94,7 +94,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
 		return PSCI_E_INVALID_ADDRESS;
 	}
 
-	stm32mp_clk_enable(RTCAPB);
+	clk_enable(RTCAPB);
 
 	cntfrq_core0 = read_cntfrq_el0();
 
@@ -104,7 +104,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
 	/* Write magic number in backup register */
 	mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
 
-	stm32mp_clk_disable(RTCAPB);
+	clk_disable(RTCAPB);
 
 	/* Generate an IT to core 1 */
 	gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 84db0219a..c92e23522 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -12,6 +12,7 @@
 
 #include <arch_helpers.h>
 #include <drivers/arm/gicv2.h>
+#include <drivers/clk.h>
 #include <drivers/st/stm32_iwdg.h>
 #include <drivers/st/stm32mp_dummy_regulator.h>
 #include <drivers/st/stm32mp_pmic.h>
@@ -214,7 +215,7 @@ void __dead2 stm32mp_plat_reset(int cpu)
 	stm32mp_mask_timer();
 
 	for (id = 0U; id < ARRAY_SIZE(tzc_source_ip); id++) {
-		if ((!stm32mp_clk_is_enabled(tzc_source_ip[id].clock_id)) ||
+		if ((!clk_is_enabled(tzc_source_ip[id].clock_id)) ||
 		    ((tzc_source_ip[id].decprot_id != STM32MP1_ETZPC_MAX_ID) &&
 		     (etzpc_get_decprot(tzc_source_ip[id].decprot_id) ==
 		      ETZPC_DECPROT_MCU_ISOLATION))) {
diff --git a/plat/st/stm32mp1/stm32mp1_scmi.c b/plat/st/stm32mp1/stm32mp1_scmi.c
index 24a8dedb5..c63e8e9c5 100644
--- a/plat/st/stm32mp1/stm32mp1_scmi.c
+++ b/plat/st/stm32mp1/stm32mp1_scmi.c
@@ -8,6 +8,7 @@
 
 #include <platform_def.h>
 
+#include <drivers/clk.h>
 #include <drivers/st/scmi-msg.h>
 #include <drivers/st/scmi.h>
 #include <drivers/st/stm32mp1_clk.h>
@@ -276,7 +277,7 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
 	if (array == NULL) {
 		*nb_elts = 1U;
 	} else if (*nb_elts == 1U) {
-		*array = stm32mp_clk_get_rate(clock->clock_id);
+		*array = clk_get_rate(clock->clock_id);
 	} else {
 		return SCMI_GENERIC_ERROR;
 	}
@@ -294,7 +295,7 @@ unsigned long plat_scmi_clock_get_rate(unsigned int agent_id,
 		return 0U;
 	}
 
-	return stm32mp_clk_get_rate(clock->clock_id);
+	return clk_get_rate(clock->clock_id);
 }
 
 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id)
@@ -325,13 +326,13 @@ int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
 	if (enable_not_disable) {
 		if (!clock->enabled) {
 			VERBOSE("SCMI clock %u enable\n", scmi_id);
-			stm32mp_clk_enable(clock->clock_id);
+			clk_enable(clock->clock_id);
 			clock->enabled = true;
 		}
 	} else {
 		if (clock->enabled) {
 			VERBOSE("SCMI clock %u disable\n", scmi_id);
-			stm32mp_clk_disable(clock->clock_id);
+			clk_disable(clock->clock_id);
 			clock->enabled = false;
 		}
 	}
@@ -474,7 +475,7 @@ void stm32mp1_init_scmi_server(void)
 			/* Sync SCMI clocks with their targeted initial state */
 			if (clk->enabled &&
 			    stm32mp_nsec_can_access_clock(clk->clock_id)) {
-				stm32mp_clk_enable(clk->clock_id);
+				clk_enable(clk->clock_id);
 			}
 		}
 
diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index aad6b6839..b1838db26 100644
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -10,6 +10,7 @@
 
 #include <common/debug.h>
 #include <drivers/arm/tzc400.h>
+#include <drivers/clk.h>
 #include <drivers/st/stm32mp1_clk.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <dt-bindings/soc/stm32mp1-tzc400.h>
@@ -106,8 +107,8 @@ static void init_tzc400(void)
  ******************************************************************************/
 static void early_init_tzc400(void)
 {
-	stm32mp_clk_enable(TZC1);
-	stm32mp_clk_enable(TZC2);
+	clk_enable(TZC1);
+	clk_enable(TZC2);
 
 	/* Region 0 set to cover all DRAM secure at 0xC000_0000 */
 	init_tzc400_begin(TZC_REGION_S_RDWR);
-- 
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