From 8d4107f0833723b49f88ed56a6c751eebc5c6696 Mon Sep 17 00:00:00 2001
From: Varun Wadekar <vwadekar@nvidia.com>
Date: Fri, 25 May 2018 15:22:58 -0700
Subject: [PATCH] Tegra194: se: fix multiple MISRA issues
This patch fixes violations for the following MISRA rules
* Rule 8.4 "A compatible declaration shall be visible when an object or
function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
conversions are perdormed shall have the same essential type
category"
* Rule 17.7 "The value returned by a function having non-void return
type shall be used"
Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---
plat/nvidia/tegra/soc/t194/drivers/se/se.c | 17 ++++++++++++-----
.../tegra/soc/t194/drivers/se/se_private.h | 4 ++--
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index 3a2e959d0..a3b338940 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -15,6 +15,7 @@
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
+#include <se.h>
#include <tegra_platform.h>
#include "se_private.h"
@@ -54,7 +55,7 @@ static bool tegra_se_is_operation_complete(void)
*/
do {
val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
- se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY);
+ se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U);
/* sleep until SE finishes */
if (se_is_busy) {
@@ -186,7 +187,8 @@ int32_t tegra_se_suspend(void)
assert(tegra_bpmp_ipc_init() == 0);
/* Enable SE clock before SE context save */
- tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+ ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+ assert(ret == 0);
/* save SE registers */
se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
@@ -201,7 +203,8 @@ int32_t tegra_se_suspend(void)
}
/* Disable SE clock after SE context save */
- tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+ ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+ assert(ret == 0);
return ret;
}
@@ -211,11 +214,14 @@ int32_t tegra_se_suspend(void)
*/
void tegra_se_resume(void)
{
+ int32_t ret = 0;
+
/* initialise communication channel with BPMP */
assert(tegra_bpmp_ipc_init() == 0);
/* Enable SE clock before SE context restore */
- tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+ ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+ assert(ret == 0);
/*
* When TZ takes over after System Resume, TZ should first reconfigure
@@ -229,5 +235,6 @@ void tegra_se_resume(void)
mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
/* Disable SE clock after SE context restore */
- tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+ ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+ assert(ret == 0);
}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
index a2c5d1c38..577217b8e 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
@@ -74,12 +74,12 @@
static inline uint32_t tegra_se_read_32(uint32_t offset)
{
- return mmio_read_32(TEGRA_SE0_BASE + offset);
+ return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset));
}
static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
{
- mmio_write_32(TEGRA_SE0_BASE + offset, val);
+ mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val);
}
#endif /* SE_PRIVATE_H */
--
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