From 9d0429a1ae3fd7eb98ba71147734e588ce0071d5 Mon Sep 17 00:00:00 2001
From: Yann Gautier <yann.gautier@st.com>
Date: Mon, 26 Oct 2020 15:21:25 +0100
Subject: [PATCH] stm32mp1: correct IO compensation disabling

In stm32mp1_syscfg_disable_io_compensation(), to disable the IO
compensation cell, we have to set the corresponding bit in
SYSCFG_CMPENCLRR register, instead of clearing the bit in SETR register.

Change-Id: I510a50451f8afb9e98c24e1ea84efbf73a39e6b4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/182085
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
---
 plat/st/stm32mp1/stm32mp1_syscfg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 34f2f1df8..62b431005 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -24,6 +24,7 @@
 #define SYSCFG_ICNR				0x1CU
 #define SYSCFG_CMPCR				0x20U
 #define SYSCFG_CMPENSETR			0x24U
+#define SYSCFG_CMPENCLRR			0x28U
 
 /*
  * SYSCFG_BOOTR Register
@@ -183,8 +184,7 @@ void stm32mp1_syscfg_disable_io_compensation(void)
 
 	mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
 
-	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
-			SYSCFG_CMPENSETR_MPU_EN);
+	mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN);
 
 	stm32mp1_clk_force_disable(SYSCFG);
 }
-- 
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