From a287d51a020bb7fad13d64c43927bf93f5e97a96 Mon Sep 17 00:00:00 2001
From: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Date: Fri, 8 Nov 2019 14:34:13 +0100
Subject: [PATCH] fdts: stm32mp1: remove PLL1 hard-coded settings
PLL1 settings are now computed from OPP table frequencies.
Change-Id: Icc8ab3975cb5e1ef4ab14796868735d39d2e5d65
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
---
fdts/stm32mp157c-ed1.dts | 8 --------
fdts/stm32mp15xx-dkx.dtsi | 8 --------
2 files changed, 16 deletions(-)
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index 17e104fe0..c08c56fe4 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -301,14 +301,6 @@
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = <2 80 0 0 0 PQR(1,0,0)>;
- frac = <0x800>;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index e56fe9b2c..036e992ba 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -291,14 +291,6 @@
CLK_LPTIM45_LSE
>;
- /* VCO = 1300.0 MHz => P = 650 (CPU) */
- pll1: st,pll@0 {
- compatible = "st,stm32mp1-pll";
- reg = <0>;
- cfg = < 2 80 0 0 0 PQR(1,0,0) >;
- frac = < 0x800 >;
- };
-
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
--
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