diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 5907c7f2ea55e41b451bb98cd232062f31ad1388..8bbef4b5e0f6113d6990ac8c46efa3abffc8eb9c 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -42,4 +42,8 @@ uint32_t stm32mp_get_ddr_ns_size(void);
 void stm32mp1_init_scmi_server(void);
 void stm32mp1_pm_save_scmi_state(uint8_t *state, size_t size);
 void stm32mp1_pm_restore_scmi_state(uint8_t *state, size_t size);
+
+#if defined(IMAGE_BL32) && DEBUG
+void stm32mp_dump_core_registers(bool fcore);
+#endif
 #endif /* STM32MP1_PRIVATE_H */
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index a01e8a5b64b76c8d5665e1069f7c21cdd9d9c2d0..a24ac81af004b2229ad876a31e2337f105edece8 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -94,6 +94,10 @@ static void stm32_sgi1_it_handler(void)
 
 	stm32mp_mask_timer();
 
+#if DEBUG
+	stm32mp_dump_core_registers(false);
+#endif
+
 	gicv2_end_of_interrupt(ARM_IRQ_SEC_SGI_1);
 
 	do {
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index e310114d88683a67180aa7adeda91bfc83826918..fc5c1183c9b9256092263c3dd81aea7a5df2a87d 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -170,7 +170,7 @@ enum ddr_type {
 #if STM32MP_SP_MIN_IN_DDR
 #define STM32MP_BL32_SIZE		U(0x00025000)	/* 148 KB for BL32 */
 #else
-#define STM32MP_BL32_SIZE		U(0x00019000)	/* 100 KB for BL32 */
+#define STM32MP_BL32_SIZE		U(0x0001A000)	/* 100 KB for BL32 */
 #endif
 #endif /* STM32MP_USE_STM32IMAGE */
 
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 7312ef6480068d3efcfc68f29c56bfec4c86961f..e9becf999a871741d861d93eebab9c94ff4a7b28 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -21,6 +21,7 @@
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
+#include <smccc_helpers.h>
 
 /* Internal layout of the 32bit OTP word board_id */
 #define BOARD_ID_BOARD_NB_MASK		GENMASK(31, 16)
@@ -801,3 +802,55 @@ bool stm32mp1_is_wakeup_from_standby(void)
 
 	return stm32_pm_context_is_valid();
 }
+
+#if defined(IMAGE_BL32) && DEBUG
+static const char *const dump_table[] = {
+	"sp_usr  ",
+	"lr_usr  ",
+	"spsr_irq",
+	"sp_irq  ",
+	"lr_irq  ",
+	"spsr_fiq",
+	"sp_fiq  ",
+	"lr_fiq  ",
+	"spsr_svc",
+	"sp_svc  ",
+	"lr_svc  ",
+	"spsr_abt",
+	"sp_abt  ",
+	"lr_abt  ",
+	"spsr_und",
+	"sp_und  ",
+	"lr_und  ",
+	"spsr_mon",
+	"sp_mon",
+	"lr_mon",
+	"scr",
+	"pmcr",
+};
+
+/*
+ * Dump CPU registers when entering in monitor.
+ */
+void stm32mp_dump_core_registers(bool fcore)
+{
+	static bool firstcore;
+	unsigned int i;
+	smc_ctx_t *ctx = smc_get_ctx(NON_SECURE);
+	uint32_t *reg = (uint32_t *)&ctx->sp_usr;
+
+	if (fcore) {
+		firstcore = true;
+	}
+
+	if (!firstcore) {
+		return;
+	}
+
+	INFO("CPU : %i\n", plat_my_core_pos());
+
+	for (i = 0U; i < ARRAY_SIZE(dump_table); i++) {
+		INFO("%s : 0x%x\n", dump_table[i], reg[i]);
+	}
+}
+#endif