From cd7795829256d989dc3aa47998b8e41c94fec336 Mon Sep 17 00:00:00 2001
From: Yann Gautier <yann.gautier@st.com>
Date: Thu, 15 Oct 2020 15:33:39 +0200
Subject: [PATCH] stm32mp1: improve binary load management with FIP
Thanks to FIP and FCONF management, remove all static
management between OPTEE and SP_MIN monitor. All binaries
except the firmware config are defined as skip. They will be
added according to the firmware configuration parsing. The same
BL2 can be used with the FIP whatever the defined monitor.
Adapt also the load sequence for standby boot.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I94ea1d29e3f0604f2790853db397411b6d516108
---
plat/st/stm32mp1/bl2_plat_setup.c | 215 +++++++-------------
plat/st/stm32mp1/include/stm32mp1_private.h | 5 +-
plat/st/stm32mp1/plat_bl2_mem_params_desc.c | 9 +-
plat/st/stm32mp1/plat_image_load.c | 36 ----
plat/st/stm32mp1/platform.mk | 2 -
plat/st/stm32mp1/stm32mp1_context.c | 37 ++--
plat/st/stm32mp1/stm32mp1_def.h | 31 ++-
plat/st/stm32mp1/stm32mp1_private.c | 6 +
8 files changed, 120 insertions(+), 221 deletions(-)
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index ba0d46582..fe5a843c9 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -163,6 +163,19 @@ void bl2_el3_early_platform_setup(u_register_t arg0,
stm32mp_save_boot_ctx_address(arg0);
}
+static int ddr_mapping_and_security(void)
+{
+ uint32_t ddr_size = dt_get_ddr_size();
+
+ if (ddr_size == 0U) {
+ return -EINVAL;
+ }
+
+ /* Map DDR for binary load, now with cacheable attribute */
+ return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
+ ddr_size, MT_MEMORY | MT_RW | MT_SECURE);
+}
+
void bl2_platform_setup(void)
{
int ret;
@@ -173,12 +186,6 @@ void bl2_platform_setup(void)
panic();
}
-#ifdef AARCH32_SP_OPTEE
- INFO("BL2 runs OP-TEE setup\n");
-#else
- INFO("BL2 runs SP_MIN setup\n");
-#endif
-
if (!stm32mp1_ddr_is_restored()) {
uint32_t bkpr_core1_magic =
tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
@@ -194,6 +201,12 @@ void bl2_platform_setup(void)
configure_pmic();
}
}
+
+ ret = ddr_mapping_and_security();
+ if (ret < 0) {
+ ERROR("DDR mapping: error %d\n", ret);
+ panic();
+ }
}
static void update_monotonic_counter(void)
@@ -529,22 +542,11 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-#if defined(AARCH32_SP_OPTEE)
bl_mem_params_node_t *bl32_mem_params;
- bl_mem_params_node_t *pager_mem_params;
- bl_mem_params_node_t *paged_mem_params;
-#endif
- const struct dyn_cfg_dtb_info_t *fw_config_info, *config_info;
- uint32_t fw_config_max_size;
- uintptr_t nsec_base_address = 0U;
- size_t nsec_size = 0U;
-#if STM32MP_SP_MIN_IN_DDR || defined(AARCH32_SP_OPTEE)
-#if STM32MP_SP_MIN_IN_DDR
+ bl_mem_params_node_t *pager_mem_params __unused;
+ bl_mem_params_node_t *paged_mem_params __unused;
+ const struct dyn_cfg_dtb_info_t *config_info;
bl_mem_params_node_t *tos_fw_mem_params;
-#endif
- uintptr_t sec_base_address = 0U;
- size_t sec_size = 0U;
-#endif
unsigned int i;
unsigned long long ddr_top __unused;
bool wakeup_ddr_sr = stm32mp1_ddr_is_restored();
@@ -552,9 +554,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
BL32_IMAGE_ID,
BL33_IMAGE_ID,
HW_CONFIG_ID,
-#if !defined(AARCH32_SP_OPTEE)
TOS_FW_CONFIG_ID,
-#endif
};
assert(bl_mem_params != NULL);
@@ -567,20 +567,8 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
switch (image_id) {
case FW_CONFIG_ID:
/* Set global DTB info for fixed fw_config information */
- fw_config_max_size = STM32MP_FW_CONFIG_MAX_SIZE;
- set_config_info(STM32MP_FW_CONFIG_BASE, fw_config_max_size, FW_CONFIG_ID);
-
- fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
- if (fw_config_info == NULL) {
- ERROR("Invalid FW_CONFIG address\n");
- plat_error_handler(-1);
- }
-
- err = fconf_populate_dtb_registry(fw_config_info->config_addr);
- if (err < 0) {
- ERROR("Parsing of FW_CONFIG failed %d\n", err);
- plat_error_handler(err);
- }
+ set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
+ fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
/* Iterate through all the fw config IDs */
for (i = 0; i < ARRAY_SIZE(image_ids); i++) {
@@ -589,8 +577,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
if (config_info == NULL) {
- ERROR("BL32_IMAGE_ID not found\n");
- plat_error_handler(-1);
+ continue;
}
bl_mem_params->image_info.image_base = config_info->config_addr;
@@ -607,28 +594,18 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
switch (image_ids[i]) {
case BL32_IMAGE_ID:
bl_mem_params->ep_info.pc = config_info->config_addr;
-#if STM32MP_SP_MIN_IN_DDR || defined(AARCH32_SP_OPTEE)
- sec_base_address += config_info->config_addr;
- sec_size += config_info->config_max_size;
-#if defined(AARCH32_SP_OPTEE)
+
/* In case of OPTEE, initialize address space with tos_fw addr */
- bl_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
- bl_mem_params->image_info.image_base = config_info->config_addr;
- bl_mem_params->image_info.image_max_size =
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ pager_mem_params->image_info.image_base = config_info->config_addr;
+ pager_mem_params->image_info.image_max_size =
config_info->config_max_size;
-#endif
-#endif
- break;
- case TOS_FW_CONFIG_ID:
-#if STM32MP_SP_MIN_IN_DDR
- if (config_info->config_addr < sec_base_address) {
- sec_size += sec_base_address - config_info->config_addr;
- sec_base_address = config_info->config_addr;
- } else {
- sec_size = config_info->config_addr - sec_base_address +
- config_info->config_max_size;
- }
-#endif
+
+ /* Init base and size for pager if exist */
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
+ (dt_get_ddr_size() - STM32MP_DDR_S_SIZE);
+ paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
break;
case BL33_IMAGE_ID:
@@ -641,105 +618,69 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
} else {
bl_mem_params->ep_info.pc = config_info->config_addr;
}
- nsec_base_address = config_info->config_addr;
- nsec_size = config_info->config_max_size;
break;
+
case HW_CONFIG_ID:
- if (config_info->config_addr < nsec_base_address) {
- nsec_size += nsec_base_address - config_info->config_addr;
- nsec_base_address = config_info->config_addr;
- } else {
- nsec_size = config_info->config_addr - nsec_base_address +
- config_info->config_max_size;
- }
+ case TOS_FW_CONFIG_ID:
break;
+
default:
return -EINVAL;
}
}
-#if defined(AARCH32_SP_OPTEE)
- /* Fix PAGEABLE part into DDR */
- bl_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
-
- if (sec_base_address < STM32MP_DDR_BASE) {
- sec_base_address = STM32MP_DDR_BASE + (dt_get_ddr_size() -
- STM32MP_DDR_S_SIZE -
- STM32MP_DDR_SHMEM_SIZE);
- sec_size = STM32MP_DDR_S_SIZE;
- bl_mem_params->image_info.image_base = sec_base_address;
- bl_mem_params->image_info.image_max_size = sec_size;
- }
-#endif
-#if STM32MP_SP_MIN_IN_DDR || defined(AARCH32_SP_OPTEE)
- err = mmap_add_dynamic_region(sec_base_address,
- sec_base_address,
- sec_size,
- MT_MEMORY | MT_RW | MT_SECURE);
- assert(err == 0);
-#endif
-
- err = mmap_add_dynamic_region(nsec_base_address,
- nsec_base_address,
- nsec_size,
- MT_MEMORY | MT_RW | MT_NS);
- assert(err == 0);
break;
- case BL32_IMAGE_ID:
-#if defined(AARCH32_SP_OPTEE)
- bl_mem_params->ep_info.pc =
- bl_mem_params->image_info.image_base;
- pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
- assert(pager_mem_params != NULL);
+ case BL32_IMAGE_ID:
+ bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
+ if (get_optee_header_ep(&bl_mem_params->ep_info, &bl_mem_params->ep_info.pc) == 1) {
+ /* BL32 is OP-TEE header */
+ if (wakeup_ddr_sr) {
+ bl_mem_params->ep_info.pc = stm32_pm_get_optee_ep();
+ if (stm32mp1_addr_inside_backupsram(bl_mem_params->ep_info.pc)) {
+ stm32mp_clk_enable(BKPSRAM);
+ }
- paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
- assert(paged_mem_params != NULL);
+ break;
+ }
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ assert((pager_mem_params != NULL) && (paged_mem_params != NULL));
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ &paged_mem_params->image_info);
+ if (err) {
+ ERROR("OPTEE header parse error.\n");
+ panic();
+ }
- err = parse_optee_header(&bl_mem_params->ep_info,
- &pager_mem_params->image_info,
- &paged_mem_params->image_info);
- if (err) {
- ERROR("OPTEE header parse error.\n");
- panic();
- }
+ /* Set optee boot info from parsed header data */
+ bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base;
+ bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
+ bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
+ } else {
+ tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
+ bl_mem_params->image_info.image_max_size +=
+ tos_fw_mem_params->image_info.image_max_size;
+ bl_mem_params->ep_info.args.arg0 = 0;
- /* Set optee boot info from parsed header data */
- bl_mem_params->ep_info.pc =
- pager_mem_params->image_info.image_base;
- bl_mem_params->ep_info.args.arg0 =
- paged_mem_params->image_info.image_base;
- bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
- bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
-#elif STM32MP_SP_MIN_IN_DDR
- tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
- bl_mem_params->image_info.image_max_size +=
- tos_fw_mem_params->image_info.image_max_size;
-
- bl_mem_params->ep_info.args.arg0 = 0;
-
- bl2_to_bl32_args.stm32_pwr_down_wfi =
- &stm32_pwr_down_wfi_wrapper;
- bl2_to_bl32_args.bl2_code_base = BL_CODE_BASE;
- bl2_to_bl32_args.bl2_code_end = BL_CODE_END;
- bl2_to_bl32_args.bl2_end = BL2_END;
- dsb();
- flush_dcache_range((uintptr_t)&bl2_to_bl32_args,
- sizeof(bl2_to_bl32_args));
-
- bl_mem_params->ep_info.args.arg3 =
- (u_register_t)&bl2_to_bl32_args;
-#else
- /* Nothing to do, BL32 is loaded together with BL2 */
+#if STM32MP_SP_MIN_IN_DDR
+ bl2_to_bl32_args.stm32_pwr_down_wfi = &stm32_pwr_down_wfi_wrapper;
+ bl2_to_bl32_args.bl2_code_base = BL_CODE_BASE;
+ bl2_to_bl32_args.bl2_code_end = BL_CODE_END;
+ bl2_to_bl32_args.bl2_end = BL2_END;
+ dsb();
+ flush_dcache_range((uintptr_t)&bl2_to_bl32_args, sizeof(bl2_to_bl32_args));
+ bl_mem_params->ep_info.args.arg3 = (u_register_t)&bl2_to_bl32_args;
#endif
+ }
break;
case BL33_IMAGE_ID:
-#ifdef AARCH32_SP_OPTEE
bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
assert(bl32_mem_params != NULL);
bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
-#endif
flush_dcache_range(bl_mem_params->image_info.image_base,
bl_mem_params->image_info.image_max_size);
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index a43b5159e..ccec2e2a6 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -30,13 +30,10 @@ void __dead2 stm32mp_wait_cpu_reset(void);
void stm32mp1_arch_security_setup(void);
void stm32mp1_security_setup(void);
-void stm32mp1_security_setup_begin(void);
-void stm32mp1_security_setup_end(void);
-void stm32mp1_security_add_region(unsigned long long region_base,
- unsigned long long region_size, bool sec);
enum boot_device_e get_boot_device(void);
+bool stm32mp1_addr_inside_backupsram(uintptr_t addr);
bool stm32mp1_is_wakeup_from_standby(void);
enum etzpc_decprot_attributes stm32mp_etzpc_binding2decprot(uint32_t mode);
diff --git a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
index c71c13b95..9d3af99c6 100644
--- a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
@@ -49,7 +49,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
- 0),
+ IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = BL33_IMAGE_ID,
},
@@ -91,7 +91,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
NON_SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t,
- 0),
+ IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
@@ -103,7 +103,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t,
- 0),
+ IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
@@ -121,7 +121,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- VERSION_2, image_info_t, 0),
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
}
diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c
index d747e467a..1744484ac 100644
--- a/plat/st/stm32mp1/plat_image_load.c
+++ b/plat/st/stm32mp1/plat_image_load.c
@@ -20,47 +20,11 @@ void plat_flush_next_bl_params(void)
flush_bl_params_desc();
}
-#ifdef AARCH32_SP_OPTEE
-static bool addr_inside_backupsram(uintptr_t addr)
-{
- return (addr >= STM32MP_BACKUP_RAM_BASE) &&
- (addr < (STM32MP_BACKUP_RAM_BASE + STM32MP_BACKUP_RAM_SIZE));
-}
-#endif
-
/*******************************************************************************
* This function returns the list of loadable images.
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
- /*
- * If going back from CSTANDBY / STANDBY and DDR was in Self-Refresh,
- * BL33 must not be loaded as it would overwrite the code already
- * in DDR. For this, the BL33 part of the bl_mem_params_desc_ptr
- * struct should be modified to skip its loading
- */
- if (stm32mp1_is_wakeup_from_standby()) {
- bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
- bl_mem_params_node_t *bl32 __unused;
- bl_mem_params_node_t *ns_dt = get_bl_mem_params_node(HW_CONFIG_ID);
-
- bl33->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
- ns_dt->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
-
-#if defined(AARCH32_SP_OPTEE)
- bl32 = get_bl_mem_params_node(BL32_IMAGE_ID);
- bl32->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
- bl32->ep_info.pc = stm32_pm_get_optee_ep();
-
- if (addr_inside_backupsram(bl32->ep_info.pc)) {
- stm32mp_clk_enable(BKPSRAM);
- }
-#else
- /* Set ep_info PC to 0, to inform BL32 it is a reset after STANDBY */
- bl33->ep_info.pc = 0;
-#endif
- }
-
return get_bl_load_info_from_mem_params_desc();
}
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 17820f144..a7f064fff 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -287,9 +287,7 @@ BL2_SOURCES += common/desc_image_load.c \
plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
plat/st/stm32mp1/plat_image_load.c
-ifeq ($(AARCH32_SP),optee)
BL2_SOURCES += lib/optee/optee_utils.c
-endif
ifeq ($(STM32MP_SP_MIN_IN_DDR),1)
BL2_SOURCES += plat/st/stm32mp1/stm32mp1_critic_power.c
diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c
index 9f8ead182..c78cb573c 100644
--- a/plat/st/stm32mp1/stm32mp1_context.c
+++ b/plat/st/stm32mp1/stm32mp1_context.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,7 +31,6 @@
#define TRAINING_AREA_SIZE 64
-#ifdef AARCH32_SP_OPTEE
/*
* OPTEE_MAILBOX_MAGIC relates to struct backup_data_s as defined
*
@@ -47,13 +46,22 @@
#define OPTEE_MAILBOX_MAGIC (OPTEE_MAILBOX_MAGIC_V2 | \
TRAINING_AREA_SIZE)
+/*
+ * TFA_MAILBOX_MAGIC relates to struct backup_data_s as defined
+ *
+ * TFA_MAILBOX_MAGIC_V1:
+ * Aligned with the OPTEE context structure V2. Identifying the BL32
+ * exchange structure with a magic.
+ */
+#define TFA_MAILBOX_MAGIC_V1 (0x1000 << 16)
+#define TFA_MAILBOX_MAGIC (TFA_MAILBOX_MAGIC_V1 | \
+ TRAINING_AREA_SIZE)
#define MAGIC_ID(magic) ((magic) & GENMASK_32(31, 16))
#define MAGIC_AREA_SIZE(magic) ((magic) & GENMASK_32(15, 0))
#if (PLAT_MAX_OPP_NB != 2) || (PLAT_MAX_PLLCFG_NB != 6)
#error OPTEE_MAILBOX_MAGIC_V1 does not support expected PLL1 settings
#endif
-#endif
/* pll_settings structure size definitions (reference to clock driver) */
#define PLL1_SETTINGS_SIZE (((PLAT_MAX_OPP_NB * \
@@ -67,26 +75,19 @@
#define SCMI_CONTEXT_SIZE (sizeof(uint8_t) * 4)
struct backup_data_s {
-#ifdef AARCH32_SP_OPTEE
uint32_t magic;
uint32_t core0_resume_hint;
uint32_t zq0cr0_zdata;
uint8_t ddr_training_backup[TRAINING_AREA_SIZE];
uint8_t pll1_settings[PLL1_SETTINGS_SIZE];
-#else
smc_ctx_t saved_smc_context[PLATFORM_CORE_COUNT];
cpu_context_t saved_cpu_context[PLATFORM_CORE_COUNT];
- uint32_t zq0cr0_zdata;
struct stm32_rtc_calendar rtc;
- uint8_t ddr_training_backup[TRAINING_AREA_SIZE];
- uint8_t pll1_settings[PLL1_SETTINGS_SIZE];
unsigned long long stgen;
uint8_t clock_cfg[CLOCK_CONTEXT_SIZE];
uint8_t scmi_context[SCMI_CONTEXT_SIZE];
-#endif
};
-#ifdef AARCH32_SP_OPTEE
uint32_t stm32_pm_get_optee_ep(void)
{
struct backup_data_s *backup_data;
@@ -115,7 +116,8 @@ uint32_t stm32_pm_get_optee_ep(void)
return ep;
}
-#else /*AARCH32_SP_OPTEE*/
+
+#if defined(IMAGE_BL32)
void stm32_clean_context(void)
{
stm32mp_clk_enable(BKPSRAM);
@@ -173,6 +175,8 @@ int stm32_save_context(uint32_t zq0cr0_zdata,
/* Context & Data to be saved at the beginning of Backup SRAM */
backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE;
+ backup_data->magic = TFA_MAILBOX_MAGIC;
+
/* Retrieve smc context struct address */
smc_context = smc_get_ctx(NON_SECURE);
@@ -264,7 +268,7 @@ unsigned long long stm32_get_stgen_from_context(void)
return stgen_cnt;
}
-#endif /*AARCH32_SP_OPTEE*/
+#endif /* IMAGE_BL32 */
uint32_t stm32_get_zdata_from_context(void)
{
@@ -283,7 +287,6 @@ uint32_t stm32_get_zdata_from_context(void)
return zdata;
}
-#ifdef AARCH32_SP_OPTEE
static int pll1_settings_in_context(struct backup_data_s *backup_data)
{
switch (MAGIC_ID(backup_data->magic)) {
@@ -293,16 +296,12 @@ static int pll1_settings_in_context(struct backup_data_s *backup_data)
assert(MAGIC_AREA_SIZE(backup_data->magic) ==
TRAINING_AREA_SIZE);
return 0;
+ case TFA_MAILBOX_MAGIC_V1:
+ return 0;
default:
panic();
}
}
-#else
-static int pll1_settings_in_context(struct backup_data_s *backup_data)
-{
- return 0;
-}
-#endif
int stm32_get_pll1_settings_from_context(void)
{
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 41efe9465..77b6534af 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -96,17 +96,7 @@
/* DDR configuration */
#define STM32MP_DDR_BASE U(0xC0000000)
#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
-#ifdef AARCH32_SP_OPTEE
-#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
-#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
-#elif STM32MP_SP_MIN_IN_DDR
-#define STM32MP_DDR_S_OFFSET U(0x10000000) /* 256 MB */
-#define STM32MP_DDR_S_SIZE U(0x00100000) /* 1 MB */
-#define STM32MP_DDR_SHMEM_SIZE U(0)
-#else
-#define STM32MP_DDR_S_SIZE U(0)
-#define STM32MP_DDR_SHMEM_SIZE U(0)
-#endif
+#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
/* DDR power initializations */
#ifndef __ASSEMBLER__
@@ -143,12 +133,11 @@ enum ddr_type {
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
+#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE
#elif STM32MP_SP_MIN_IN_DDR
#define STM32MP_BL32_SIZE U(0x00025000) /* 148 KB for BL32 */
#define STM32MP_BL32_BIN_SIZE (STM32MP_BL32_SIZE + \
STM32MP_BL32_DTB_SIZE)
-#define STM32MP_BL32_BASE (STM32MP_DDR_BASE + \
- STM32MP_DDR_S_OFFSET)
#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
@@ -172,13 +161,17 @@ enum ddr_type {
/* BL2 and BL32/sp_min require finer granularity tables */
#if defined(IMAGE_BL2)
- #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
+ #if STM32MP_USB_PROGRAMMER
+ #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
+ #else
+ #define MAX_XLAT_TABLES U(3) /* 12 KB for mapping */
+ #endif
#elif defined(IMAGE_BL32)
-#if STM32MP_SP_MIN_IN_DDR
-#define MAX_XLAT_TABLES U(6) /* 20 KB for mapping */
-#else
-#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
-#endif
+ #if STM32MP_SP_MIN_IN_DDR
+ #define MAX_XLAT_TABLES U(6) /* 24 KB for mapping */
+ #else
+ #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
+ #endif
#endif
/*
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 4d375542f..1bca5863d 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -749,6 +749,12 @@ int plat_bind_regulator(struct stm32mp_regulator *regu)
return 0;
}
+bool stm32mp1_addr_inside_backupsram(uintptr_t addr)
+{
+ return (addr >= STM32MP_BACKUP_RAM_BASE) &&
+ (addr < (STM32MP_BACKUP_RAM_BASE + STM32MP_BACKUP_RAM_SIZE));
+}
+
bool stm32mp1_is_wakeup_from_standby(void)
{
return (stm32mp_get_boot_action() == BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY);
--
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