From ed264fa979731d35523f7c8b998f8ae855644f3e Mon Sep 17 00:00:00 2001 From: Yann Gautier <yann.gautier@st.com> Date: Fri, 6 Nov 2020 15:32:25 +0100 Subject: [PATCH] tzc400: correct FAIL_CONTROL Privileged bit When bit 20 of TZC400 Fail control register is set to 1, it means Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this. Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e Signed-off-by: Yann Gautier <yann.gautier@st.com> Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/183494 Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com> Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com> Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com> --- include/drivers/arm/tzc400.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index 32aeb0350..c94d96425 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h @@ -65,8 +65,8 @@ #define FAIL_CONTROL_NS_SECURE U(0) #define FAIL_CONTROL_NS_NONSECURE U(1) #define FAIL_CONTROL_PRIV_SHIFT 20 -#define FAIL_CONTROL_PRIV_PRIV U(0) -#define FAIL_CONTROL_PRIV_UNPRIV U(1) +#define FAIL_CONTROL_PRIV_UNPRIV U(0) +#define FAIL_CONTROL_PRIV_PRIV U(1) /* * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. -- GitLab