From f7a4819c34b811206e389ad3c50b6b9b18652f32 Mon Sep 17 00:00:00 2001
From: Yann Gautier <yann.gautier@st.com>
Date: Thu, 20 Aug 2020 09:43:34 +0200
Subject: [PATCH] stm32mp1: use FCONF to configure product mapping
Add FW_CONFIG device tree files for all boards. The file content is for
the moment common to all boards. It describes where the different images
will be loaded.
Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
fdts/stm32mp15-ddr-1g-fw-config.dts | 47 +++++
fdts/stm32mp15-ddr-512m-fw-config.dts | 47 +++++
fdts/stm32mp157a-avenger96-fw-config.dts | 6 +
fdts/stm32mp157a-dk1-fw-config.dts | 6 +
fdts/stm32mp157a-ed1-fw-config.dts | 6 +
fdts/stm32mp157a-ev1-fw-config.dts | 6 +
fdts/stm32mp157c-dk2-fw-config.dts | 6 +
fdts/stm32mp157c-ed1-fw-config.dts | 6 +
fdts/stm32mp157c-ev1-fw-config.dts | 6 +
fdts/stm32mp157d-dk1-fw-config.dts | 6 +
fdts/stm32mp157d-ed1-fw-config.dts | 6 +
fdts/stm32mp157d-ev1-fw-config.dts | 6 +
fdts/stm32mp157f-dk2-fw-config.dts | 6 +
fdts/stm32mp157f-ed1-fw-config.dts | 6 +
fdts/stm32mp157f-ev1-fw-config.dts | 6 +
plat/st/common/bl2_io_storage.c | 9 +
plat/st/stm32mp1/bl2_plat_setup.c | 188 ++++++++++++++------
plat/st/stm32mp1/plat_bl2_mem_params_desc.c | 40 ++---
plat/st/stm32mp1/plat_image_load.c | 23 ++-
plat/st/stm32mp1/platform.mk | 8 +
plat/st/stm32mp1/sp_min/sp_min_setup.c | 46 +++--
plat/st/stm32mp1/stm32mp1_def.h | 16 +-
22 files changed, 398 insertions(+), 104 deletions(-)
create mode 100644 fdts/stm32mp15-ddr-1g-fw-config.dts
create mode 100644 fdts/stm32mp15-ddr-512m-fw-config.dts
create mode 100644 fdts/stm32mp157a-avenger96-fw-config.dts
create mode 100644 fdts/stm32mp157a-dk1-fw-config.dts
create mode 100644 fdts/stm32mp157a-ed1-fw-config.dts
create mode 100644 fdts/stm32mp157a-ev1-fw-config.dts
create mode 100644 fdts/stm32mp157c-dk2-fw-config.dts
create mode 100644 fdts/stm32mp157c-ed1-fw-config.dts
create mode 100644 fdts/stm32mp157c-ev1-fw-config.dts
create mode 100644 fdts/stm32mp157d-dk1-fw-config.dts
create mode 100644 fdts/stm32mp157d-ed1-fw-config.dts
create mode 100644 fdts/stm32mp157d-ev1-fw-config.dts
create mode 100644 fdts/stm32mp157f-dk2-fw-config.dts
create mode 100644 fdts/stm32mp157f-ed1-fw-config.dts
create mode 100644 fdts/stm32mp157f-ev1-fw-config.dts
diff --git a/fdts/stm32mp15-ddr-1g-fw-config.dts b/fdts/stm32mp15-ddr-1g-fw-config.dts
new file mode 100644
index 000000000..822f55e12
--- /dev/null
+++ b/fdts/stm32mp15-ddr-1g-fw-config.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+#include <dt-bindings/soc/stm32mp1-tzc400.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ hw-config {
+ load-address = <0x0 0xC0600000>;
+ max-size = <0x00020000>;
+ id = <HW_CONFIG_ID>;
+ };
+
+ nt_fw {
+ load-address = <0x0 0xC0100000>;
+ max-size = <0x00400000>;
+ id = <BL33_IMAGE_ID>;
+ };
+
+#ifdef AARCH32_SP_OPTEE
+ tos_fw {
+ load-address = <0x0 0x2FFC0000>;
+ max-size = <0x0001F000>;
+ id = <BL32_IMAGE_ID>;
+ };
+#else
+ tos_fw {
+ load-address = <0x0 0x2FFC0000>;
+ max-size = <0x00019000>;
+ id = <BL32_IMAGE_ID>;
+ };
+
+ tos_fw-config {
+ load-address = <0x0 0x2FFD9000>;
+ max-size = <0x00005000>;
+ id = <TOS_FW_CONFIG_ID>;
+ };
+#endif
+ };
+};
diff --git a/fdts/stm32mp15-ddr-512m-fw-config.dts b/fdts/stm32mp15-ddr-512m-fw-config.dts
new file mode 100644
index 000000000..822f55e12
--- /dev/null
+++ b/fdts/stm32mp15-ddr-512m-fw-config.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+#include <dt-bindings/soc/stm32mp1-tzc400.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ hw-config {
+ load-address = <0x0 0xC0600000>;
+ max-size = <0x00020000>;
+ id = <HW_CONFIG_ID>;
+ };
+
+ nt_fw {
+ load-address = <0x0 0xC0100000>;
+ max-size = <0x00400000>;
+ id = <BL33_IMAGE_ID>;
+ };
+
+#ifdef AARCH32_SP_OPTEE
+ tos_fw {
+ load-address = <0x0 0x2FFC0000>;
+ max-size = <0x0001F000>;
+ id = <BL32_IMAGE_ID>;
+ };
+#else
+ tos_fw {
+ load-address = <0x0 0x2FFC0000>;
+ max-size = <0x00019000>;
+ id = <BL32_IMAGE_ID>;
+ };
+
+ tos_fw-config {
+ load-address = <0x0 0x2FFD9000>;
+ max-size = <0x00005000>;
+ id = <TOS_FW_CONFIG_ID>;
+ };
+#endif
+ };
+};
diff --git a/fdts/stm32mp157a-avenger96-fw-config.dts b/fdts/stm32mp157a-avenger96-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157a-avenger96-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157a-dk1-fw-config.dts b/fdts/stm32mp157a-dk1-fw-config.dts
new file mode 100644
index 000000000..256d0db93
--- /dev/null
+++ b/fdts/stm32mp157a-dk1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-512m-fw-config.dts"
diff --git a/fdts/stm32mp157a-ed1-fw-config.dts b/fdts/stm32mp157a-ed1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157a-ed1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157a-ev1-fw-config.dts b/fdts/stm32mp157a-ev1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157a-ev1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157c-dk2-fw-config.dts b/fdts/stm32mp157c-dk2-fw-config.dts
new file mode 100644
index 000000000..256d0db93
--- /dev/null
+++ b/fdts/stm32mp157c-dk2-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-512m-fw-config.dts"
diff --git a/fdts/stm32mp157c-ed1-fw-config.dts b/fdts/stm32mp157c-ed1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157c-ed1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157c-ev1-fw-config.dts b/fdts/stm32mp157c-ev1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157c-ev1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157d-dk1-fw-config.dts b/fdts/stm32mp157d-dk1-fw-config.dts
new file mode 100644
index 000000000..256d0db93
--- /dev/null
+++ b/fdts/stm32mp157d-dk1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-512m-fw-config.dts"
diff --git a/fdts/stm32mp157d-ed1-fw-config.dts b/fdts/stm32mp157d-ed1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157d-ed1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157d-ev1-fw-config.dts b/fdts/stm32mp157d-ev1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157d-ev1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157f-dk2-fw-config.dts b/fdts/stm32mp157f-dk2-fw-config.dts
new file mode 100644
index 000000000..256d0db93
--- /dev/null
+++ b/fdts/stm32mp157f-dk2-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-512m-fw-config.dts"
diff --git a/fdts/stm32mp157f-ed1-fw-config.dts b/fdts/stm32mp157f-ed1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157f-ed1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/fdts/stm32mp157f-ev1-fw-config.dts b/fdts/stm32mp157f-ev1-fw-config.dts
new file mode 100644
index 000000000..10f9402c4
--- /dev/null
+++ b/fdts/stm32mp157f-ev1-fw-config.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp15-ddr-1g-fw-config.dts"
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index c8226ad9a..683196d3d 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -105,6 +105,10 @@ static const io_dev_connector_t *spi_dev_con;
static const io_dev_connector_t *memmap_dev_con;
#endif
+static const io_uuid_spec_t fw_config_uuid_spec = {
+ .uuid = UUID_FW_CONFIG,
+};
+
static const io_uuid_spec_t bl33_partition_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33
};
@@ -216,6 +220,11 @@ static const struct plat_io_policy policies[] = {
.image_spec = (uintptr_t)&bl33_partition_spec,
.check = open_image
},
+ [FW_CONFIG_ID] = {
+ .dev_handle = &image_dev_handle,
+ .image_spec = (uintptr_t)&fw_config_uuid_spec,
+ .check = open_image
+ },
[TOS_FW_CONFIG_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&tos_fw_config_uuid_spec,
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 0ab94b10a..f0e95175c 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -5,6 +5,7 @@
*/
#include <assert.h>
+#include <errno.h>
#include <string.h>
#include <platform_def.h>
@@ -26,6 +27,8 @@
#include <drivers/st/stm32mp1_pwr.h>
#include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stpmic1.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/mmio.h>
#include <lib/optee_utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
@@ -159,7 +162,6 @@ void bl2_el3_early_platform_setup(u_register_t arg0,
void bl2_platform_setup(void)
{
int ret;
- uint32_t ddr_ns_size;
ret = stm32mp1_ddr_probe();
if (ret < 0) {
@@ -167,26 +169,8 @@ void bl2_platform_setup(void)
panic();
}
- ddr_ns_size = stm32mp_get_ddr_ns_size();
- assert(ddr_ns_size > 0U);
-
- /* Map non secure DDR for BL33 load, now with cacheable attribute */
- ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
- ddr_ns_size, MT_MEMORY | MT_RW | MT_NS);
- assert(ret == 0);
-
#ifdef AARCH32_SP_OPTEE
INFO("BL2 runs OP-TEE setup\n");
-
- /* Map secure DDR for OP-TEE paged area */
- ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size,
- STM32MP_DDR_BASE + ddr_ns_size,
- STM32MP_DDR_S_SIZE,
- MT_MEMORY | MT_RW | MT_SECURE);
- assert(ret == 0);
-
- /* Initialize tzc400 after DDR initialization */
- stm32mp1_security_setup();
#else
INFO("BL2 runs SP_MIN setup\n");
#endif
@@ -532,33 +516,6 @@ skip_console_init:
stm32mp_io_setup();
}
-#if defined(AARCH32_SP_OPTEE)
-static void set_mem_params_info(entry_point_info_t *ep_info,
- image_info_t *unpaged, image_info_t *paged)
-{
- uintptr_t bl32_ep = 0;
-
- /* Use the default dram setup if no valid ep found */
- if (get_optee_header_ep(ep_info, &bl32_ep) &&
- (bl32_ep >= STM32MP_OPTEE_BASE) &&
- (bl32_ep < (STM32MP_OPTEE_BASE + STM32MP_OPTEE_SIZE))) {
- assert((STM32MP_OPTEE_BASE >= BL2_LIMIT) ||
- ((STM32MP_OPTEE_BASE + STM32MP_OPTEE_SIZE) <= BL2_BASE));
-
- unpaged->image_base = STM32MP_OPTEE_BASE;
- unpaged->image_max_size = STM32MP_OPTEE_SIZE;
- } else {
- unpaged->image_base = STM32MP_DDR_BASE + dt_get_ddr_size() -
- STM32MP_DDR_S_SIZE -
- STM32MP_DDR_SHMEM_SIZE;
- unpaged->image_max_size = STM32MP_DDR_S_SIZE;
- }
- paged->image_base = STM32MP_DDR_BASE + dt_get_ddr_size() -
- STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
- paged->image_max_size = STM32MP_DDR_S_SIZE;
-}
-#endif
-
/*******************************************************************************
* This function can be used by the platforms to update/use image
* information for given `image_id`.
@@ -572,6 +529,24 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
bl_mem_params_node_t *pager_mem_params;
bl_mem_params_node_t *paged_mem_params;
#endif
+ const struct dyn_cfg_dtb_info_t *fw_config_info, *config_info;
+ uint32_t fw_config_max_size;
+ uintptr_t nsec_base_address = 0U;
+ size_t nsec_size = 0U;
+#if defined(AARCH32_SP_OPTEE)
+ uintptr_t sec_base_address = 0U;
+ size_t sec_size = 0U;
+#endif
+ unsigned int i;
+ unsigned long long ddr_top __unused;
+ const unsigned int image_ids[] = {
+ BL32_IMAGE_ID,
+ BL33_IMAGE_ID,
+ HW_CONFIG_ID,
+#if !defined(AARCH32_SP_OPTEE)
+ TOS_FW_CONFIG_ID,
+#endif
+ };
assert(bl_mem_params != NULL);
@@ -581,6 +556,123 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
#endif
switch (image_id) {
+ case FW_CONFIG_ID:
+ /* Set global DTB info for fixed fw_config information */
+ fw_config_max_size = STM32MP_FW_CONFIG_MAX_SIZE;
+ set_config_info(STM32MP_FW_CONFIG_BASE, fw_config_max_size, FW_CONFIG_ID);
+
+ fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+ if (fw_config_info == NULL) {
+ ERROR("Invalid FW_CONFIG address\n");
+ plat_error_handler(-1);
+ }
+
+ err = fconf_populate_dtb_registry(fw_config_info->config_addr);
+ if (err < 0) {
+ ERROR("Parsing of FW_CONFIG failed %d\n", err);
+ plat_error_handler(err);
+ }
+
+ /* Iterate through all the fw config IDs */
+ for (i = 0; i < ARRAY_SIZE(image_ids); i++) {
+ bl_mem_params = get_bl_mem_params_node(image_ids[i]);
+ assert(bl_mem_params != NULL);
+
+ config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
+ if (config_info == NULL) {
+ ERROR("BL32_IMAGE_ID not found\n");
+ plat_error_handler(-1);
+ }
+
+ bl_mem_params->image_info.image_base = config_info->config_addr;
+ bl_mem_params->image_info.image_max_size = config_info->config_max_size;
+
+ switch (image_ids[i]) {
+ case BL32_IMAGE_ID:
+ bl_mem_params->ep_info.pc = config_info->config_addr;
+#if defined(AARCH32_SP_OPTEE)
+ sec_base_address += config_info->config_addr;
+ sec_size += config_info->config_max_size;
+
+ /* In case of OPTEE, initialize address space with tos_fw addr */
+ bl_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ bl_mem_params->image_info.image_base = config_info->config_addr;
+ bl_mem_params->image_info.image_max_size =
+ config_info->config_max_size;
+#endif
+ break;
+ case TOS_FW_CONFIG_ID:
+ break;
+ case BL33_IMAGE_ID:
+ if (!wakeup_standby) {
+ bl_mem_params->ep_info.pc = config_info->config_addr;
+ }
+ nsec_base_address = config_info->config_addr;
+ nsec_size = config_info->config_max_size;
+ break;
+ case HW_CONFIG_ID:
+ if (config_info->config_addr < nsec_base_address) {
+ nsec_size += nsec_base_address - config_info->config_addr;
+ nsec_base_address = config_info->config_addr;
+ } else {
+ nsec_size = config_info->config_addr - nsec_base_address +
+ config_info->config_max_size;
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+#if defined(AARCH32_SP_OPTEE)
+ /* Fix PAGEABLE part into DDR */
+ bl_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+
+ if (sec_base_address < STM32MP_DDR_BASE) {
+ sec_base_address = STM32MP_DDR_BASE + (dt_get_ddr_size() -
+ STM32MP_DDR_S_SIZE -
+ STM32MP_DDR_SHMEM_SIZE);
+ sec_size = STM32MP_DDR_S_SIZE;
+ bl_mem_params->image_info.image_base = sec_base_address;
+ bl_mem_params->image_info.image_max_size = sec_size;
+ }
+
+ err = mmap_add_dynamic_region(sec_base_address,
+ sec_base_address,
+ sec_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ assert(err == 0);
+#endif
+
+ err = mmap_add_dynamic_region(nsec_base_address,
+ nsec_base_address,
+ nsec_size,
+ MT_MEMORY | MT_RW | MT_NS);
+ assert(err == 0);
+
+ /* Configuration of TZC400 */
+ stm32mp1_security_setup_begin();
+
+#if defined(AARCH32_SP_OPTEE)
+ stm32mp1_security_add_region(sec_base_address, sec_size, true);
+
+ if (sec_base_address > STM32MP_DDR_BASE) {
+ stm32mp1_security_add_region(STM32MP_DDR_BASE,
+ sec_base_address - STM32MP_DDR_BASE,
+ false);
+ }
+
+ ddr_top = STM32MP_DDR_BASE + dt_get_ddr_size() - 1U;
+ if (sec_base_address + sec_size < ddr_top) {
+ stm32mp1_security_add_region(sec_base_address + sec_size,
+ ddr_top - (sec_base_address + sec_size) + 1U,
+ false);
+ }
+#else
+ stm32mp1_security_add_region(STM32MP_DDR_BASE, dt_get_ddr_size(), false);
+#endif
+ stm32mp1_security_setup_end();
+
+ break;
case BL32_IMAGE_ID:
#if defined(AARCH32_SP_OPTEE)
bl_mem_params->ep_info.pc =
@@ -592,10 +684,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
assert(paged_mem_params != NULL);
- set_mem_params_info(&bl_mem_params->ep_info,
- &pager_mem_params->image_info,
- &paged_mem_params->image_info);
-
err = parse_optee_header(&bl_mem_params->ep_info,
&pager_mem_params->image_info,
&paged_mem_params->image_info);
diff --git a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
index b9e74229d..dcafb8c3a 100644
--- a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
@@ -19,6 +19,21 @@
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ /* Fill FW_CONFIG related information if it exists */
+ {
+ .image_id = FW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_PLAT_SETUP),
+
+ .image_info.image_base = STM32MP_FW_CONFIG_BASE,
+ .image_info.image_max_size = STM32MP_FW_CONFIG_MAX_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
/* Fill BL32 related information */
{
.image_id = BL32_IMAGE_ID,
@@ -27,24 +42,14 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
VERSION_2, entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
-#if !defined(AARCH32_SP_OPTEE)
- .ep_info.pc = STM32MP_BL32_BASE,
-#endif
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
- IMAGE_ATTRIB_PLAT_SETUP),
-#if defined(AARCH32_SP_OPTEE)
- /* optee header is loaded in SYSRAM above BL2 */
- .image_info.image_base = STM32MP_OPTEE_BASE,
- .image_info.image_max_size = STM32MP_OPTEE_SIZE,
-#else
- .image_info.image_base = STM32MP_BL32_BASE,
- .image_info.image_max_size = STM32MP_BL32_SIZE,
-#endif
+ 0),
+
.next_handoff_image_id = BL33_IMAGE_ID,
},
@@ -88,10 +93,6 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
VERSION_2, image_info_t,
0),
- .image_info.image_base = STM32MP_HW_CONFIG_BASE,
- .image_info.image_max_size =
- PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_HW_CONFIG_BASE,
-
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#if !defined(AARCH32_SP_OPTEE)
@@ -104,8 +105,6 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
VERSION_2, image_info_t,
0),
- .image_info.image_base = STM32MP_BL32_DTB_BASE,
- .image_info.image_max_size = STM32MP_BL32_DTB_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#endif
@@ -117,7 +116,6 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
VERSION_2, entry_point_info_t,
NON_SECURE | EXECUTABLE),
- .ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
@@ -125,10 +123,6 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
- .image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
- .image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
- (PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
-
.next_handoff_image_id = INVALID_IMAGE_ID,
}
};
diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c
index 120cabc25..a5afbe4e5 100644
--- a/plat/st/stm32mp1/plat_image_load.c
+++ b/plat/st/stm32mp1/plat_image_load.c
@@ -33,14 +33,7 @@ static bool addr_inside_backupsram(uintptr_t addr)
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
-#ifdef AARCH32_SP_OPTEE
- bl_mem_params_node_t *bl32 = get_bl_mem_params_node(BL32_IMAGE_ID);
-#endif
- bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
- uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size();
uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
- uint32_t bkpr_core1_addr =
- tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
uintptr_t pwr_base = stm32mp_pwr_base();
/*
@@ -52,12 +45,22 @@ bl_load_info_t *plat_get_bl_image_load_info(void)
if (stm32mp_boot_action_is_wakeup_from_standby() &&
((mmio_read_32(pwr_base + PWR_CR3) & PWR_CR3_DDRSREN) != 0U) &&
((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U)) {
+ uint32_t bkpr_core1_addr =
+ tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
+
stm32mp_clk_enable(RTCAPB);
if (mmio_read_32(bkpr_core1_addr) != 0U) {
+ bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
+ bl_mem_params_node_t *bl32 __unused;
+ bl_mem_params_node_t *ns_dt __unused;
+
bl33->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
-#ifdef AARCH32_SP_OPTEE
+ ns_dt = get_bl_mem_params_node(HW_CONFIG_ID);
+ ns_dt->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
+#if AARCH32_SP_OPTEE
+ bl32 = get_bl_mem_params_node(BL32_IMAGE_ID);
bl32->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING;
bl32->ep_info.pc = stm32_pm_get_optee_ep();
@@ -76,10 +79,6 @@ bl_load_info_t *plat_get_bl_image_load_info(void)
stm32mp_clk_disable(RTCAPB);
}
- /* Max size is non-secure DDR end address minus image_base */
- bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size -
- bl33->image_info.image_base;
-
return get_bl_load_info_from_mem_params_desc();
}
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index d1ff12db7..eb64db88d 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -89,6 +89,11 @@ STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c
STM32MP_NT_FW_CONFIG := ${BL33_CFG}
+STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
+STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
+FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_NT_FW_CONFIG},--hw-config))
ifeq ($(AARCH32_SP),sp_min)
@@ -183,6 +188,9 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
plat/st/stm32mp1/stm32mp1_security.c \
plat/st/stm32mp1/stm32mp1_syscfg.c
+BL2_SOURCES += lib/fconf/fconf.c \
+ lib/fconf/fconf_dyn_cfg_getter.c
+
BL2_SOURCES += drivers/io/io_block.c \
drivers/io/io_dummy.c \
drivers/io/io_fip.c \
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index bc385b5b4..737a6abe2 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -290,32 +290,47 @@ static void stm32mp1_etzpc_early_setup(void)
etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE);
}
-static void populate_ns_dt(u_register_t ns_dt_addr)
+static void populate_ns_dt(u_register_t ns_dt_addr, uintptr_t sec_base, size_t sec_size)
{
void *external_fdt = (void *)ns_dt_addr;
int ret;
+ if (sec_base < STM32MP_DDR_BASE) {
+ /* No need to reserve memory if secure monitor is not in DDR */
+ return;
+ }
+
+ /* Map Base Non Secure DDR for Non secure DT update */
+ ret = mmap_add_dynamic_region(ns_dt_addr, ns_dt_addr, STM32MP_HW_CONFIG_MAX_SIZE,
+ MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_RW | MT_NS);
+ assert(ret == 0);
+
if (fdt_check_header(external_fdt) != 0) {
INFO("Non-secure device tree not found\n");
- return;
+ goto out;
}
ret = fdt_open_into(external_fdt, external_fdt, STM32MP_HW_CONFIG_MAX_SIZE);
if (ret < 0) {
WARN("Error opening DT %i\n", ret);
+ goto out;
}
- ret = fdt_add_reserved_memory(external_fdt, "tf-a", BL_CODE_BASE,
- (BL32_LIMIT + STM32MP_BL32_DTB_SIZE) - BL_CODE_BASE);
+ ret = fdt_add_reserved_memory(external_fdt, "tf-a", sec_base, sec_size);
if (ret < 0) {
WARN("Error updating DT %i\n", ret);
+ goto out;
}
ret = fdt_pack(external_fdt);
if (ret < 0) {
WARN("Error packing DT %i\n", ret);
}
+
+out:
+ ret = mmap_remove_dynamic_region(ns_dt_addr, STM32MP_HW_CONFIG_MAX_SIZE);
+ assert(ret == 0);
}
/*******************************************************************************
@@ -365,6 +380,9 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
+ uintptr_t dt_addr = arg1;
+ uintptr_t sec_base = 0U;
+ size_t sec_size = 0U;
/* Imprecise aborts can be masked in NonSecure */
write_scr(read_scr() | SCR_AW_BIT);
@@ -381,11 +399,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
bl_params_node_t *bl_params = params_from_bl2->head;
- /*
- * Copy BL33 entry point information.
- * They are stored in Secure RAM, in BL2's address space.
- */
while (bl_params != NULL) {
+ /*
+ * Copy BL33 entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
if (bl_params->image_id == BL33_IMAGE_ID) {
bl33_image_ep_info = *bl_params->ep_info;
/*
@@ -397,14 +415,17 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
bl33_image_ep_info.args.arg1 = 0U;
bl33_image_ep_info.args.arg2 = arg2;
}
+ }
- break;
+ if (bl_params->image_id == BL32_IMAGE_ID) {
+ sec_base = bl_params->image_info->image_base;
+ sec_size = bl_params->image_info->image_max_size;
}
bl_params = bl_params->next_params_info;
}
- if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
+ if (dt_open_and_check(dt_addr) < 0) {
panic();
}
@@ -421,7 +442,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
stm32mp1_etzpc_early_setup();
if (arg2 != 0U) {
- populate_ns_dt(arg2);
+ populate_ns_dt(arg2, sec_base, sec_size);
} else {
INFO("Non-secure device tree not found\n");
}
@@ -475,9 +496,6 @@ void sp_min_platform_setup(void)
{
ddr_save_sr_mode();
- /* Initialize tzc400 after DDR initialization */
- stm32mp1_security_setup();
-
generic_delay_timer_init();
stm32_gic_init();
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 29e2c2626..8faf6d79e 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -127,20 +127,22 @@ enum ddr_type {
#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
STM32MP_OPTEE_BASE)
-#define STM32MP_BL2_SIZE U(0x0001A000) /* 104 KB for BL2 */
+#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
#else
-#define STM32MP_BL32_SIZE U(0x00018000) /* 92 KB for BL32 */
+#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */
#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL32_SIZE)
-#define STM32MP_BL2_SIZE U(0x0001E000) /* 100 KB for BL2 */
-#define STM32MP_BL2_BASE (STM32MP_BL32_DTB_BASE - \
+#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
+
+#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
+ STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
#endif
@@ -179,8 +181,12 @@ enum ddr_type {
#define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE
#endif
+#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
+ STM32MP_SYSRAM_SIZE - \
+ PAGE_SIZE)
+#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
#define STM32MP_HW_CONFIG_BASE STM32MP_DDR_BASE
-#define STM32MP_HW_CONFIG_MAX_SIZE U(0x10000)
+#define STM32MP_HW_CONFIG_MAX_SIZE U(0x20000)
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
/* Define Temporary Stack size use during low power mode */
--
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