- 21 Jul, 2020 3 commits
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Sebastien Pasdeloup authored
Signed-off-by:Sebastien Pasdeloup <sebastien.pasdeloup-ext@st.com> Change-Id: I94e710365ae3516df939b339c795cba8c364f94b
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Lionel Debieve authored
Calibration uses the ARM counter which is 32 bit signed value. Depending on the clock source, some required timing value cannot be reached and must be limited to the INT32 max value. Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Change-Id: If499d33b42c6abebd40b3d7947aa6f709fdeab8e Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/171274 Reviewed-by:
CITOOLS <smet-aci-reviews@lists.codex.cro.st.com> Reviewed-by:
Yann GAUTIER <yann.gautier@st.com> Reviewed-by:
CIBUILD <smet-aci-builds@lists.codex.cro.st.com> Reviewed-by:
Etienne CARRIERE <etienne.carriere@st.com> (cherry picked from commit b353ba7c) Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/171688 Reviewed-by:
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Lionel Debieve authored
Avoid possible lock when the capture is not stable. Base the capture value to a define threshold. Signed-off-by:
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- 02 Jul, 2020 1 commit
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Yann Gautier authored
When coming back from STANDBY, nothing has to be loaded from storage devices, as the DDR was in Self-Refresh, and all the code is already there. BL32 image load is also explicitly skipped. Change-Id: I960a757c95f216f0325ddbd7842b54d0b80f5848 Signed-off-by:
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- 03 Jun, 2020 1 commit
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Lionel Debieve authored
Signed-off-by:
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- 02 Jun, 2020 1 commit
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Lionel Debieve authored
Increase delay from 10µs to 50µs to avoid panic or DDR corruption after self refresh exit sequence. Signed-off-by:
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- 04 May, 2020 6 commits
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Yann Gautier authored
Do not try to set a regulator voltage if the previous value is not correct. Change-Id: I0a89600ca34b4509bf9c059f4fb23471ba4b96eb Signed-off-by:
Nicolas LE BAYON <nicolas.le.bayon@st.com> Reviewed-by:
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Yann Gautier authored
Correct smatch warning: drivers/st/pmic/stm32mp_pmic.c:143 pmic_config_boot_on() error: uninitialized symbol 'status'. Change-Id: Ib6d8beaf2069c8a60bfa0eb1c0631db984bccf4b Signed-off-by:
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Yann Gautier authored
Use errno values, or the return of called functions, instead of -1. Change-Id: If7b53de5cbfb4d2c9979bce0e594dd92bf07a77a Signed-off-by:
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Yann Gautier authored
Correct smatch issue: drivers/st/clk/stm32mp_clkfunc.c:379 fdt_get_uart_clock_freq() warn: unsigned 'clk_id' is never less than zero. Change-Id: Ie33d886c0f991c2e387fd213393c442d473eae55 Signed-off-by:
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Yann Gautier authored
This issue was found with cppcheck in our downstream code: [drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]: (warning) Either the condition 'buffer!=0U' is redundant or there is possible null pointer dereference: local_buffer. Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9 Signed-off-by:
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Yann Gautier authored
This warning was issued by cppcheck in our downstream code: [plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]: (warning) Identical condition 'node<0', second condition is always false The second test has to check variable pwr_regulators_node. Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f Signed-off-by:
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- 08 Apr, 2020 1 commit
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Bernard Puel authored
Add contributing guide to STMicroelectronics/arm-trusted-firmware repository. Change-Id: I35578a640c86c3cd2118a691293d3968425d7bb7 Signed-off-by:
Bernard Puel <bernard.puel@st.com> Signed-off-by:
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- 12 Mar, 2020 6 commits
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Nicolas Le Bayon authored
Define DDR Self Refresh (SR) mode read/set/save/restore API functions. When entering in cstop/cstandby, switch to SSR (Software). When exiting, go back to the saved mode. Change-Id: I3d47b2a68043a8f9889de184f571fa5fa4b724f2 Signed-off-by:
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Nicolas Le Bayon authored
Remove unused stm32mp_ddr_supports_ssr_asr(), since this support is enabled by DDR settings defined in DT. Change-Id: I9c3a812e93de363e50498ec8b38b3829723e4194 Signed-off-by:
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Nicolas Le Bayon authored
DDR Self Refresh mode capabilities are related to DDR settings defined in DT and not to DDR type. So remove checking this before executing a Self Refresh mode transition. Change-Id: I49831975311542b062f5084c7ff4cf105789cc36 Signed-off-by:
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Nicolas Le Bayon authored
Remove unused service for setting DDR Self Refresh (SR) mode since it could conflict with the one selected at boot time. Change-Id: Icd8bbf986fe53ae9d9b892454405addc417cf05d Signed-off-by:
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Nicolas Le Bayon authored
Prevent power leakage by setting CPU supply to minimum voltage defined in device tree when entering in CSTOP. When exiting, set nomimal OPP voltage using saved PLL1 settings. Change-Id: Icdba66185176b30ad83103d3927bf23d106fca32 Signed-off-by:
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Nicolas Le Bayon authored
Replace hard-coded regulator names by stm32mp_get_cpu_supply_name() platform service which gets CPU regulator name from DT and finds its related supply name. Change-Id: Iae0da6e04335e0c7d65e84a01f8dfadddb2ce83c Signed-off-by:
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- 11 Mar, 2020 4 commits
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Nicolas Le Bayon authored
dt_get_cpu_regulator_name() parses DT and retrieves the CPU regulator name, so that software is easily able to get/set its voltage. CPU0 is taken as reference, because it's active in both single and multi core configurations. Change-Id: Id7077c5adfa39074ec643dbbac89942e46f2893f Signed-off-by:
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Nicolas Le Bayon authored
This change adds CPU0 node in STM32MP15x DTS and the regulator related the the CPU. It allows software to get CPU0 regulator name and to handle voltage get/set operations. Change-Id: Ieb11331b5189ecc416354cc547bb45356416e558 Signed-off-by:
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Nicolas Le Bayon authored
dt_pmic_find_supply() finds the supply name related to a regulator name. pmic_set_regulator_min_voltage() sets target supply to its min voltage specified in the FDT by property "regulator-min-microvolt". Change-Id: I9a1184aca715877d4f1c5b73696c880722a8d502 Signed-off-by:
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Nicolas Le Bayon authored
In pmic_operate(), "regulators" node value must be checked before entering in the fdt_for_each_subnode loop. Change-Id: If0d80b2f08e3fb4727dd722af2167ebdbfc409cc Signed-off-by:
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- 06 Mar, 2020 3 commits
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Yann Gautier authored
The GPIOGEN is used for default UART4 crash console. For other platforms, other GPIO could be used for the UART TX. Add all the possible defines. Change-Id: Ic379bdac062aba32796fcf8532031058e2a86e68 Signed-off-by:
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Nicolas Le Bayon authored
Introduce stm32mp1_clk_opp_get_voltage_from_freq() which returns the VDDCORE regulator voltage corresponding to the input OPP frequency. The PLL1 settings structure is parsed to get this value. Change-Id: Ice5c58d65be4540f64dd855028a4e34a26445d7c Signed-off-by:
Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by:
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Nicolas Le Bayon authored
MPUDIV dividers are stored in a constant array, under bit shifts form. They must be used in this way by the clock driver. Change-Id: Ib22485f0a3d66297ed0e3bafbf980054ed9afcf0 Signed-off-by:
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- 04 Mar, 2020 2 commits
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Nicolas Le Bayon authored
When setting boot-on regulator, the voltage register is only re-programmed if the read value in PMIC is not in the range provided in DT. The dt_pmic_get_regulator_voltage() function is updated to read both min and max voltage values. The macro CMD_GET_VOLTAGE is renamed to CMD_GET_MIN_VOLTAGE to reflect what it really does. Change-Id: I8056e625e50ccf26ab32b2b84634bf53b840d9ac Signed-off-by:
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Yann Gautier authored
If GPIO port for UART TX is less than 8, the register GPIO_AFRL should be used to set the alternate. GPIO_AFRH is used if GPIO port is greater or equal to 8. The macro GPIO_TX_ALT_SHIFT is removed and the GPIO port number is tested against GPIO_ALT_LOWER_LIMIT (=8) in plat_crash_console_init() function. Change-Id: Ibb62223ed6bce589bbcab59a5e986b2677e6d118 Signed-off-by:
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- 25 Feb, 2020 1 commit
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Lionel Debieve authored
The stm32_gic_enable_spi function is returning the interrupt id from the device tree. The fix properly checks the return error. Moving the initialization status to shared and secured and put the DT interrupt accordingly. Signed-off-by:
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- 19 Feb, 2020 1 commit
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Nicolas Le Bayon authored
configure_pmic() is in charge of setting voltages and enabling regulators if they are defined in DT with "boot-on" or "always-on" properties. This is done one after the other. It has to be executed after DDR initialization, which setups its own regulator rampings, with specified order and delays. Change-Id: I6d32ebb849ee469adfc83544491bd5f7f52fa042 Signed-off-by:
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- 11 Feb, 2020 1 commit
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Yann Gautier authored
Set correctly the .PHONY targets and update dependencies for stm32image. STM32_TF_STM32 is a real target file, no need to be .PHONY. Change-Id: I3d6c23a6c468c1da39eec78f518d5fa3a33ad1d7 Signed-off-by:
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- 29 Jan, 2020 9 commits
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Lionel Debieve authored
Signed-off-by: -
Lionel Debieve authored
In case of USB boot mode, SRAM is mapped and it requires a new translation table. Mandatory for 512MB boards. Signed-off-by:
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Nicolas Le Bayon authored
Comparing index and loop counter with the same type is easier and avoids to check index value. Change-Id: Ic3c0b71bdd5fc6b6187053eeee71a1a661147d44 Signed-off-by:
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Antonio Borneo authored
The variable stm32image_header is declared with global visibility but is use in one function only. Move it as local variable in the function. Signed-off-by:
Antonio Borneo <antonio.borneo@st.com> Change-Id: Idfcfc39ea4415deb8c4e09640494e4d4a944523b Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/154762 Reviewed-by:
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Antonio Borneo authored
Don't force the base of strtol, since it's able to select the base automatically depending on the prefix of the value. This does not breaks the current build script that extracts the addresses, including the 0x prefix, from the map file. This change helps using stm32image in shell scripts where the addresses can be computed using the shell arithmetic expansion "$((...))", that produces a value in base decimal. Signed-off-by:
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Antonio Borneo authored
Three header fields are not properly converted to little endian before assignment, resulting in incorrect header while executing stm32image on big endian hosts. Convert the value of the header fields version_number, image_checksum and edcsa_algorithm to little endian before the assignment. Signed-off-by:
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Yann Gautier authored
On highly parallel builds, sometimes the stm32image tool is not correctly compiled, with a 'File truncated' error. Re-order makefile rules to compile it before TF-A binaries. Change-Id: Ie61a6a837b51643811c776fc981cebbbeda662ab Signed-off-by:
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Yann Gautier authored
DTB and BL32 area should not be set as executable in MMU during BL2 execution, hence set those areas as MT_RO_DATA. Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db Signed-off-by:
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Yann Gautier authored
This change avoids speculative accesses to DDR whereas it is not reachable and could lead to bus stall. To achieve this the dynamic mapping in MMU is used. A first mapping is done for DDR init with MT_NON_CACHEABLE attribute. Once DDR access is setup, it is unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by:
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