From 094b10cb795a85e2f90f03c24b030888ab2f1fa3 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Thu, 17 Mar 2022 23:58:43 +0100
Subject: [PATCH] dt-bindings: gnss: Add two more chips
The CSR GSD4t is a CSR product using the SiRFstarIV core, and
the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV
core.
These chips have a SRESETN line that can be pulled low to hard
reset the chip and in some designs this is connected to a GPIO,
so add this as an optional property.
Update the example with a reset line so users see that it need
to be tagged as active low.
Cc: devicetree@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220317225844.1262643-4-linus.walleij@linaro.org
---
Documentation/devicetree/bindings/gnss/sirfstar.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/gnss/sirfstar.yaml b/Documentation/devicetree/bindings/gnss/sirfstar.yaml
index 1178d4b32a5cf..991599cdaa6b0 100644
--- a/Documentation/devicetree/bindings/gnss/sirfstar.yaml
+++ b/Documentation/devicetree/bindings/gnss/sirfstar.yaml
@@ -25,6 +25,8 @@ allOf:
properties:
compatible:
enum:
+ - csr,gsd4t
+ - csr,csrg05ta03-icje-r
- fastrax,uc430
- linx,r4
- wi2wi,w2sg0004
@@ -39,6 +41,11 @@ properties:
description:
Main voltage regulator, pin names such as 3V3_IN, VCC, VDD.
+ reset-gpios:
+ maxItems: 1
+ description: An optional active low reset line, should be flagged with
+ GPIO_ACTIVE_LOW.
+
sirf,onoff-gpios:
maxItems: 1
description: GPIO used to power on and off device, pin name ON_OFF.
@@ -61,6 +68,7 @@ examples:
gnss {
compatible = "wi2wi,w2sg0084i";
vcc-supply = <&gnss_vcc_reg>;
+ reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
current-speed = <38400>;
--
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