diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..8f49a1ae03f14cddfec7e5e7b6ec4a51a7198502
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-audclk.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 Audio Clock Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7100-audclk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Audio source clock
+ - description: External 12.288MHz clock
+ - description: Domain 7 AHB bus clock
+
+ clock-names:
+ items:
+ - const: audio_src
+ - const: audio_12288
+ - const: dom7ahb_bus
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive-jh7100.h>
+
+ clock-controller@10480000 {
+ compatible = "starfive,jh7100-audclk";
+ reg = <0x10480000 0x10000>;
+ clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
+ <&clkgen JH7100_CLK_AUDIO_12288>,
+ <&clkgen JH7100_CLK_DOM7AHB_BUS>;
+ clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
+ #clock-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ef38d9ab650004fe4f1592629adcfa591ac91d1..56891a9da798bb29c9243280601bd1d6a35a0926 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18430,12 +18430,12 @@ M: Ion Badulescu <ionut@badula.org>
S: Odd Fixes
F: drivers/net/ethernet/adaptec/starfire*
-STARFIVE JH7100 CLOCK DRIVER
+STARFIVE JH7100 CLOCK DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained
-F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
-F: drivers/clk/starfive/clk-starfive-jh7100.c
-F: include/dt-bindings/clock/starfive-jh7100.h
+F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
+F: drivers/clk/starfive/clk-starfive-jh7100*
+F: include/dt-bindings/clock/starfive-jh7100*.h
STARFIVE JH7100 PINCTRL DRIVER
M: Emil Renner Berthing <kernel@esmil.dk>
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2f0d40b7c346c6868faa968cc80085b073cc70e6..a46a8a949ad5cc588c583cfa09e0886e50cf34ec 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -232,6 +232,7 @@ config COMMON_CLK_GEMINI
config COMMON_CLK_LAN966X
bool "Generic Clock Controller driver for LAN966X SoC"
+ depends on SOC_LAN966 || COMPILE_TEST
help
This driver provides support for Generic Clock Controller(GCK) on
LAN966X SoC. GCK generates and supplies clock to various peripherals
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 57d06e183dff4e1230d3375688073ba53dffd099..c69a7e2f06457dbf21f3153aa30ab80ba3d7397c 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -95,7 +95,7 @@
static const struct clk_pll_table clk_audio_pll_table[] = {
{ 0, 45158400 }, { 1, 49152000 },
- { 0, 0 },
+ { /* sentinel */ }
};
/* pll clocks */
@@ -138,46 +138,46 @@ static struct clk_factor_table sd_factor_table[] = {
{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
{ 280, 1, 25 * 128 },
- { 0, 0, 0 },
+ { /* sentinel */ }
};
static struct clk_factor_table de_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
{ 8, 1, 12 },
- { 0, 0, 0 },
+ { /* sentinel */ }
};
static struct clk_factor_table hde_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
- { 0, 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table rmii_ref_div_table[] = {
{ 0, 4 }, { 1, 10 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table std12rate_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
{ 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table i2s_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
{ 8, 24 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table nand_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
{ 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
{ 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
- { 0, 0 },
+ { /* sentinel */ }
};
/* mux clock */
diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
index a2f34d13fb54304357eed076ceb11e31863e76d2..3e48105602aa06017179ec4e18aeab8b4018f96d 100644
--- a/drivers/clk/actions/owl-s700.c
+++ b/drivers/clk/actions/owl-s700.c
@@ -73,7 +73,7 @@
static struct clk_pll_table clk_audio_pll_table[] = {
{0, 45158400}, {1, 49152000},
- {0, 0},
+ { /* sentinel */ }
};
static struct clk_pll_table clk_cvbs_pll_table[] = {
@@ -82,7 +82,8 @@ static struct clk_pll_table clk_cvbs_pll_table[] = {
{33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000},
{36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000},
{39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000},
- {42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0},
+ {42, 44 * 12000000}, {43, 45 * 12000000},
+ { /* sentinel */ }
};
/* pll clocks */
@@ -137,7 +138,7 @@ static struct clk_factor_table sd_factor_table[] = {
{276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
{280, 1, 25 * 128}, {281, 1, 26 * 128},
- {0, 0},
+ { /* sentinel */ }
};
static struct clk_factor_table lcd_factor_table[] = {
@@ -150,18 +151,19 @@ static struct clk_factor_table lcd_factor_table[] = {
{256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
{260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
{264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
- {0, 0},
+ { /* sentinel */ }
};
static struct clk_div_table hdmia_div_table[] = {
{0, 1}, {1, 2}, {2, 3}, {3, 4},
{4, 6}, {5, 8}, {6, 12}, {7, 16},
{8, 24},
- {0, 0},
+ { /* sentinel */ }
};
static struct clk_div_table rmii_div_table[] = {
{0, 4}, {1, 10},
+ { /* sentinel */ }
};
/* divider clocks */
@@ -178,13 +180,14 @@ static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2,
static struct clk_factor_table de_factor_table[] = {
{0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
{4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
- {8, 1, 12}, {0, 0, 0},
+ {8, 1, 12},
+ { /* sentinel */ }
};
static struct clk_factor_table hde_factor_table[] = {
{0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
{4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
- {0, 0, 0},
+ { /* sentinel */ }
};
/* gate clocks */
diff --git a/drivers/clk/actions/owl-s900.c b/drivers/clk/actions/owl-s900.c
index 790890978424a241c8229c7592c2843b1fdb694d..7dc6e07fb60ea7ea90fe868b0a66d9f2fbb85812 100644
--- a/drivers/clk/actions/owl-s900.c
+++ b/drivers/clk/actions/owl-s900.c
@@ -73,12 +73,12 @@
static struct clk_pll_table clk_audio_pll_table[] = {
{ 0, 45158400 }, { 1, 49152000 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_pll_table clk_edp_pll_table[] = {
{ 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
- { 0, 0 },
+ { /* sentinel */ }
};
/* pll clocks */
@@ -120,41 +120,41 @@ static struct clk_div_table nand_div_table[] = {
{ 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
{ 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
{ 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table apb_div_table[] = {
{ 1, 2 }, { 2, 3 }, { 3, 4 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table eth_mac_div_table[] = {
{ 0, 2 }, { 1, 4 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table rmii_ref_div_table[] = {
{ 0, 4 }, { 1, 10 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table usb3_mac_div_table[] = {
{ 1, 2 }, { 2, 3 }, { 3, 4 },
- { 0, 8 },
+ { /* sentinel */ }
};
static struct clk_div_table i2s_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
{ 8, 24 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_div_table hdmia_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
{ 8, 24 },
- { 0, 0 },
+ { /* sentinel */ }
};
/* divider clocks */
@@ -185,24 +185,24 @@ static struct clk_factor_table sd_factor_table[] = {
{ 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
{ 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
- { 0, 0 },
+ { /* sentinel */ }
};
static struct clk_factor_table dmm_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
{ 4, 1, 4 },
- { 0, 0, 0 },
+ { /* sentinel */ }
};
static struct clk_factor_table noc_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
- { 0, 0, 0 },
+ { /* sentinel */ }
};
static struct clk_factor_table bisp_factor_table[] = {
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
- { 0, 0, 0 },
+ { /* sentinel */ }
};
/* factor clocks */
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 2d65770d8665171a69ebe1b8b9cd4fa9ca831d57..fdc9b669f8a7af22f12e7c08cf98a02182533875 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -535,7 +535,7 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
/*
* Assume that if it has already been selected (for example by the
- * bootloader), enough time has aready passed.
+ * bootloader), enough time has already passed.
*/
if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
osc->prepared = true;
diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
index f95959ff85aca0d854e890e2d8a726be173b6a45..a3f349d4624d004d3a730cbe6a2deda3a6a602ad 100644
--- a/drivers/clk/axis/clk-artpec6.c
+++ b/drivers/clk/axis/clk-artpec6.c
@@ -2,7 +2,7 @@
/*
* ARTPEC-6 clock initialization
*
- * Copyright 2015-2016 Axis Comunications AB.
+ * Copyright 2015-2016 Axis Communications AB.
*/
#include <linux/clk-provider.h>
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 3667b4d731e71494039e5a74da857aafd7012dde..3ad20e75fd23f6b7e60de0b59b87f52285f66736 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -939,10 +939,8 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
u32 unused_frac_mask =
GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
- u64 rem;
u32 div, mindiv, maxdiv;
- rem = do_div(temp, rate);
div = temp;
div &= ~unused_frac_mask;
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index a48ddd3e0b28cd40b0c4cc998e4e1d8c586bdf67..d7e5b94bed45181acfd9e649a4f4997633ac1b0c 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -89,7 +89,7 @@
* Parameters for VCO frequency configuration
*
* VCO frequency =
- * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
+ * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv)
*/
struct iproc_pll_vco_param {
unsigned long rate;
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
index e65eeef9cbaf16ad3ba4238f0f17a12e70eb6915..5dd65164c8b1b3185ffa08363cb8c54992e8d08d 100644
--- a/drivers/clk/bcm/clk-kona-setup.c
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -510,7 +510,7 @@ static bool kona_clk_valid(struct kona_clk *bcm_clk)
* placeholders for non-supported clocks. Keep track of the
* position of each clock name in the original array.
*
- * Allocates an array of pointers to to hold the names of all
+ * Allocates an array of pointers to hold the names of all
* non-null entries in the original array, and returns a pointer to
* that array in *names. This will be used for registering the
* clock with the common clock code. On successful return,
diff --git a/drivers/clk/clk-clps711x.c b/drivers/clk/clk-clps711x.c
index a2c6486ef1708bb387fd88b33e8bbd1fd04c730d..f8417ee2961aaabc9c46e9007716d83b25a3c7bc 100644
--- a/drivers/clk/clk-clps711x.c
+++ b/drivers/clk/clk-clps711x.c
@@ -28,11 +28,13 @@ static const struct clk_div_table spi_div_table[] = {
{ .val = 1, .div = 8, },
{ .val = 2, .div = 2, },
{ .val = 3, .div = 1, },
+ { /* sentinel */ }
};
static const struct clk_div_table timer_div_table[] = {
{ .val = 0, .div = 256, },
{ .val = 1, .div = 1, },
+ { /* sentinel */ }
};
struct clps711x_clk {
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 4274540327cece5b2428b794a815c55a95ff06cc..8efa5142ff8c725ff4a1522b97785a4aed994a96 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -34,7 +34,7 @@
* and assume that the IP, that needs m and n, has also its own
* prescaler, which is capable to divide by 2^scale. In this way
* we get the denominator to satisfy the desired range (2) and
- * at the same time much much better result of m and n than simple
+ * at the same time a much better result of m and n than simple
* saturated values.
*/
diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
index 78d5ea669fea7df4aba3dfa5b9c337b37b1ece81..cda5e258355bc68419c117c1934df5ac7652be32 100644
--- a/drivers/clk/clk-oxnas.c
+++ b/drivers/clk/clk-oxnas.c
@@ -209,15 +209,11 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct oxnas_stdclk_data *data;
- const struct of_device_id *id;
struct regmap *regmap;
int ret;
int i;
- id = of_match_device(oxnas_stdclk_dt_ids, &pdev->dev);
- if (!id)
- return -ENODEV;
- data = id->data;
+ data = of_device_get_match_data(&pdev->dev);
regmap = syscon_node_to_regmap(of_get_parent(np));
if (IS_ERR(regmap)) {
diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index 071f5a1c8a1ce6bfc8bc8f147ca5189d7a918d1e..41851f41b68211a6dab2b076403ad3b4965f42a1 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -655,7 +655,7 @@ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
f = synth->data->freq_vco;
f *= n_den >> 4;
- /* Now we need to to 64-bit division: f/n_num */
+ /* Now we need to do 64-bit division: f/n_num */
/* And compensate for the 4 bits we dropped */
f = div64_u64(f, (n_num >> 4));
diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
index 56012a3d02192efdb63df7df51b23525b66562ee..9ea1a80acbe8b5be6475d2f729e5609c0a61d3a9 100644
--- a/drivers/clk/hisilicon/clk-hi3559a.c
+++ b/drivers/clk/hisilicon/clk-hi3559a.c
@@ -611,8 +611,8 @@ static struct hisi_mux_clock hi3559av100_shub_mux_clks[] = {
/* shub div clk */
-static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}};
-static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}};
+static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}, {/*sentinel*/}};
+static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}, {/*sentinel*/}};
static struct hisi_divider_clock hi3559av100_shub_div_clks[] = {
{ HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2,
diff --git a/drivers/clk/loongson1/clk-loongson1c.c b/drivers/clk/loongson1/clk-loongson1c.c
index 703f87622cf5f7042c216a27b5842ec83e146a99..1ebf740380efbd38f6a912e59e3488c4fc76a2e9 100644
--- a/drivers/clk/loongson1/clk-loongson1c.c
+++ b/drivers/clk/loongson1/clk-loongson1c.c
@@ -37,6 +37,7 @@ static const struct clk_div_table ahb_div_table[] = {
[1] = { .val = 1, .div = 4 },
[2] = { .val = 2, .div = 3 },
[3] = { .val = 3, .div = 3 },
+ [4] = { /* sentinel */ }
};
void __init ls1x_clk_init(void)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index cd0f5bae24d49ae4b443ca6a82e10bb005c9137f..8f3b7a94a66773f9e6ee2f4ca46f9d31e24b11f3 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -2232,7 +2232,7 @@ static struct clk_regmap meson8b_vpu_1 = {
};
/*
- * The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
+ * The VPU clock has two identical clock trees (vpu_0 and vpu_1)
* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
* actually manage this glitch-free mux because it does top-to-bottom
* updates the each clock tree and switches to the "inactive" one when
diff --git a/drivers/clk/mmp/pwr-island.c b/drivers/clk/mmp/pwr-island.c
index ab57c0e995c1d03bdebfeebeae311eb380bcfc97..edaa2433a472adf00b3c8c8ac71cefb3786df59a 100644
--- a/drivers/clk/mmp/pwr-island.c
+++ b/drivers/clk/mmp/pwr-island.c
@@ -76,7 +76,7 @@ static int mmp_pm_domain_power_off(struct generic_pm_domain *genpd)
if (pm_domain->lock)
spin_lock_irqsave(pm_domain->lock, flags);
- /* Turn off and isolate the the power island. */
+ /* Turn off and isolate the power island. */
val = readl(pm_domain->reg);
val &= ~pm_domain->power_on;
val &= ~0x100;
diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c
index 431b55bb0d2f796544ab3245d2dde822b2ea0b1d..cf3af88d4021417534e72cd617ec3f6d719fc9c7 100644
--- a/drivers/clk/qcom/gcc-sm6125.c
+++ b/drivers/clk/qcom/gcc-sm6125.c
@@ -4151,7 +4151,7 @@ static int gcc_sm6125_probe(struct platform_device *pdev)
/*
* Enable DUAL_EDGE mode for MCLK RCGs
- * This is requierd to enable MND divider mode
+ * This is required to enable MND divider mode
*/
regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000);
regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000);
diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index 32567795765fb5bb6b03a05e50614f065171ded1..3930d922efb4d32192dc0c83e3dfa474df79f116 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017, Intel Corporation
*/
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index cbabde2b476bf38db29d228c1fdf0ed415b1acd5..f5c1ca42b66866539a9cab6b0fa025061af267b4 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017, Intel Corporation
*/
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index e444e4a0ee53e2b0047e0d8e411682d896012fd6..1d82737befd33932eb0f9f8551fca73147d6a6da 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017, Intel Corporation
*/
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 4e508a844b3da60e5398c27c8c2756df33120fb0..9b2e0275fbf781da76fe9511904817a233e32556 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017, Intel Corporation
*/
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index c0fa9d5e641fe240a1ec469d4ddd5e511351bb78..003bd2d56ce7eaa47f28a92eda7b49e86d3c96d9 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -7,3 +7,11 @@ config CLK_STARFIVE_JH7100
help
Say yes here to support the clock controller on the StarFive JH7100
SoC.
+
+config CLK_STARFIVE_JH7100_AUDIO
+ tristate "StarFive JH7100 audio clock support"
+ depends on CLK_STARFIVE_JH7100
+ default m if SOC_STARFIVE
+ help
+ Say Y or M here to support the audio clocks on the StarFive JH7100
+ SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 09759cc735307f42024d78e62cda94d65f7170f0..0fa8ecb9ec1c6116b383886715043299b1431eea 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
# StarFive Clock
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
+obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
new file mode 100644
index 0000000000000000000000000000000000000000..8473a65e219be732f8f2c6e9d67149ed2f4d03ae
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7100 Audio Clock Driver
+ *
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7100-audio.h>
+
+#include "clk-starfive-jh7100.h"
+
+/* external clocks */
+#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
+#define JH7100_AUDCLK_AUDIO_12288 (JH7100_AUDCLK_END + 1)
+#define JH7100_AUDCLK_DOM7AHB_BUS (JH7100_AUDCLK_END + 2)
+#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD (JH7100_AUDCLK_END + 3)
+#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD (JH7100_AUDCLK_END + 4)
+#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD (JH7100_AUDCLK_END + 5)
+#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
+#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
+
+static const struct jh7100_clk_data jh7100_audclk_data[] = {
+ JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
+ JH7100_AUDCLK_ADC_MCLK,
+ JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
+ JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
+ JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
+ JH7100_AUDCLK_I2SADC_BCLK_N,
+ JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
+ JH7100_AUDCLK_I2SADC_BCLK),
+ JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
+ JH7100_AUDCLK_DAC_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
+ JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
+ JH7100_AUDCLK_I2S1_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
+ JH7100_AUDCLK_I2S1_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
+ JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
+ JH7100_AUDCLK_I2S1_BCLK_N,
+ JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
+ JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
+ JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
+ JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
+ JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
+ JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
+ JH7100_AUDCLK_VAD_INTMEM,
+ JH7100_AUDCLK_AUDIO_12288),
+};
+
+static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh7100_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7100_AUDCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7100_audclk_probe(struct platform_device *pdev)
+{
+ struct jh7100_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
+ u32 max = jh7100_audclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7100_audclk_data[idx].name,
+ .ops = starfive_jh7100_clk_ops(max),
+ .parent_data = parents,
+ .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+ .flags = jh7100_audclk_data[idx].flags,
+ };
+ struct jh7100_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7100_audclk_data[idx].parents[i];
+
+ if (pidx < JH7100_AUDCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JH7100_AUDCLK_AUDIO_SRC)
+ parents[i].fw_name = "audio_src";
+ else if (pidx == JH7100_AUDCLK_AUDIO_12288)
+ parents[i].fw_name = "audio_12288";
+ else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS)
+ parents[i].fw_name = "dom7ahb_bus";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH7100_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(priv->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv);
+}
+
+static const struct of_device_id jh7100_audclk_match[] = {
+ { .compatible = "starfive,jh7100-audclk" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7100_audclk_match);
+
+static struct platform_driver jh7100_audclk_driver = {
+ .probe = jh7100_audclk_probe,
+ .driver = {
+ .name = "clk-starfive-jh7100-audio",
+ .of_match_table = jh7100_audclk_match,
+ },
+};
+module_platform_driver(jh7100_audclk_driver);
+
+MODULE_AUTHOR("Emil Renner Berthing");
+MODULE_DESCRIPTION("StarFive JH7100 audio clock driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 25d31afa0f871a598fd4aa0ceca5271c29d4c09a..691aeebc709278eff145ed07cbeffdbb70d10704 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -20,69 +20,15 @@
#include <dt-bindings/clock/starfive-jh7100.h>
+#include "clk-starfive-jh7100.h"
+
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1)
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
-/* register fields */
-#define JH7100_CLK_ENABLE BIT(31)
-#define JH7100_CLK_INVERT BIT(30)
-#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
-#define JH7100_CLK_MUX_SHIFT 24
-#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
-
-/* clock data */
-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
- .name = _name, \
- .flags = CLK_SET_RATE_PARENT | (_flags), \
- .max = JH7100_CLK_ENABLE, \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = _max, \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7100_CLK_ENABLE | (_max), \
- .parents = { [0] = _parent }, \
-}
-
-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
- .parents = { __VA_ARGS__ }, \
-}
-
-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7100_CLK_ENABLE | \
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
- .parents = { __VA_ARGS__ }, \
-}
-
-#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
- .name = _name, \
- .flags = CLK_SET_RATE_PARENT, \
- .max = JH7100_CLK_INVERT, \
- .parents = { [0] = _parent }, \
-}
-
-static const struct {
- const char *name;
- unsigned long flags;
- u32 max;
- u8 parents[4];
-} jh7100_clk_data[] __initconst = {
+static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
@@ -225,7 +171,7 @@ static const struct {
JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_USBPHY_PLLDIV25M),
- JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT),
+ JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
@@ -323,21 +269,6 @@ static const struct {
JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
};
-struct jh7100_clk {
- struct clk_hw hw;
- unsigned int idx;
- unsigned int max_div;
-};
-
-struct jh7100_clk_priv {
- /* protect clk enable and set rate/parent from happening at the same time */
- spinlock_t rmw_lock;
- struct device *dev;
- void __iomem *base;
- struct clk_hw *pll[3];
- struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
-};
-
static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
{
return container_of(hw, struct jh7100_clk, hw);
@@ -399,22 +330,13 @@ static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
return div ? parent_rate / div : 0;
}
-static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk,
- unsigned long rate, unsigned long parent)
-{
- unsigned long max = clk->max_div;
- unsigned long div = DIV_ROUND_UP(parent, rate);
-
- return min(div, max);
-}
-
static int jh7100_clk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct jh7100_clk *clk = jh7100_clk_from(hw);
unsigned long parent = req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
- unsigned long div = jh7100_clk_bestdiv(clk, rate, parent);
+ unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
unsigned long result = parent / div;
/*
@@ -442,12 +364,56 @@ static int jh7100_clk_set_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate);
+ unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
+ 1UL, (unsigned long)clk->max_div);
jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
return 0;
}
+static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 reg = jh7100_clk_reg_get(clk);
+ unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
+ ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
+
+ return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
+}
+
+static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ unsigned long parent100 = 100 * req->best_parent_rate;
+ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
+ JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
+ unsigned long result = parent100 / div100;
+
+ /* clamp the result as in jh7100_clk_determine_rate() above */
+ if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
+ result = parent100 / (div100 + 1);
+ if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
+ result = parent100 / (div100 - 1);
+
+ req->rate = result;
+ return 0;
+}
+
+static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
+ JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
+ u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
+ return 0;
+}
+
static u8 jh7100_clk_get_parent(struct clk_hw *hw)
{
struct jh7100_clk *clk = jh7100_clk_from(hw);
@@ -534,6 +500,13 @@ static const struct clk_ops jh7100_clk_div_ops = {
.debug_init = jh7100_clk_debug_init,
};
+static const struct clk_ops jh7100_clk_fdiv_ops = {
+ .recalc_rate = jh7100_clk_frac_recalc_rate,
+ .determine_rate = jh7100_clk_frac_determine_rate,
+ .set_rate = jh7100_clk_frac_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
static const struct clk_ops jh7100_clk_gdiv_ops = {
.enable = jh7100_clk_enable,
.disable = jh7100_clk_disable,
@@ -561,17 +534,45 @@ static const struct clk_ops jh7100_clk_gmux_ops = {
.debug_init = jh7100_clk_debug_init,
};
+static const struct clk_ops jh7100_clk_mdiv_ops = {
+ .recalc_rate = jh7100_clk_recalc_rate,
+ .determine_rate = jh7100_clk_determine_rate,
+ .get_parent = jh7100_clk_get_parent,
+ .set_parent = jh7100_clk_set_parent,
+ .set_rate = jh7100_clk_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_gmd_ops = {
+ .enable = jh7100_clk_enable,
+ .disable = jh7100_clk_disable,
+ .is_enabled = jh7100_clk_is_enabled,
+ .recalc_rate = jh7100_clk_recalc_rate,
+ .determine_rate = jh7100_clk_determine_rate,
+ .get_parent = jh7100_clk_get_parent,
+ .set_parent = jh7100_clk_set_parent,
+ .set_rate = jh7100_clk_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
static const struct clk_ops jh7100_clk_inv_ops = {
.get_phase = jh7100_clk_get_phase,
.set_phase = jh7100_clk_set_phase,
.debug_init = jh7100_clk_debug_init,
};
-static const struct clk_ops *__init jh7100_clk_ops(u32 max)
+const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
{
if (max & JH7100_CLK_DIV_MASK) {
+ if (max & JH7100_CLK_MUX_MASK) {
+ if (max & JH7100_CLK_ENABLE)
+ return &jh7100_clk_gmd_ops;
+ return &jh7100_clk_mdiv_ops;
+ }
if (max & JH7100_CLK_ENABLE)
return &jh7100_clk_gdiv_ops;
+ if (max == JH7100_CLK_FRAC_MAX)
+ return &jh7100_clk_fdiv_ops;
return &jh7100_clk_div_ops;
}
@@ -586,6 +587,7 @@ static const struct clk_ops *__init jh7100_clk_ops(u32 max)
return &jh7100_clk_inv_ops;
}
+EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
{
@@ -607,7 +609,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
unsigned int idx;
int ret;
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL);
if (!priv)
return -ENOMEM;
@@ -637,7 +639,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_clk_data[idx].name,
- .ops = jh7100_clk_ops(max),
+ .ops = starfive_jh7100_clk_ops(max),
.parent_data = parents,
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
.flags = jh7100_clk_data[idx].flags,
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h
new file mode 100644
index 0000000000000000000000000000000000000000..f116be5740a5f148d454d30fbd5cfaf10b1ccc29
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7100.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_JH7100_H
+#define __CLK_STARFIVE_JH7100_H
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+
+/* register fields */
+#define JH7100_CLK_ENABLE BIT(31)
+#define JH7100_CLK_INVERT BIT(30)
+#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
+#define JH7100_CLK_MUX_SHIFT 24
+#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
+#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
+#define JH7100_CLK_FRAC_SHIFT 8
+#define JH7100_CLK_INT_MASK GENMASK(7, 0)
+
+/* fractional divider min/max */
+#define JH7100_CLK_FRAC_MIN 100UL
+#define JH7100_CLK_FRAC_MAX 25599UL
+
+/* clock data */
+struct jh7100_clk_data {
+ const char *name;
+ unsigned long flags;
+ u32 max;
+ u8 parents[4];
+};
+
+#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = CLK_SET_RATE_PARENT | (_flags), \
+ .max = JH7100_CLK_ENABLE, \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = _max, \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH7100_CLK_ENABLE | (_max), \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = JH7100_CLK_FRAC_MAX, \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH7100_CLK_ENABLE | \
+ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH7100_CLK_ENABLE | \
+ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = CLK_SET_RATE_PARENT, \
+ .max = JH7100_CLK_INVERT, \
+ .parents = { [0] = _parent }, \
+}
+
+struct jh7100_clk {
+ struct clk_hw hw;
+ unsigned int idx;
+ unsigned int max_div;
+};
+
+struct jh7100_clk_priv {
+ /* protect clk enable and set rate/parent from happening at the same time */
+ spinlock_t rmw_lock;
+ struct device *dev;
+ void __iomem *base;
+ struct clk_hw *pll[3];
+ struct jh7100_clk reg[];
+};
+
+const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
+
+#endif
diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c
index 74c1d894cca864f0045c05826be93996c52cbddc..219c80653dbdb2e32ed9e9d0602e8b6cc5c90be7 100644
--- a/drivers/clk/tegra/clk-tegra124-emc.c
+++ b/drivers/clk/tegra/clk-tegra124-emc.c
@@ -198,6 +198,7 @@ static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
tegra->emc = platform_get_drvdata(pdev);
if (!tegra->emc) {
+ put_device(&pdev->dev);
pr_err("%s: cannot find EMC driver\n", __func__);
return NULL;
}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 5ca1e39dd88a6ae5777299a88ba0ab56d4bb9e0a..2c6315cfd5c6b259338deae1978f790ad6d6e31d 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -6,8 +6,7 @@ clk-common = dpll.o composite.o divider.o gate.o \
fixed-factor.o mux.o apll.o \
clkt_dpll.o clkt_iclk.o clkt_dflt.o \
clkctrl.o
-obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \
- clk-33xx-compat.o
+obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
@@ -18,9 +17,9 @@ obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
clk-dra7-atl.o dpll3xxx.o \
- dpll44xx.o clk-7xx-compat.o
-obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \
- clk-43xx-compat.o
+ dpll44xx.o
+
+obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
endif # CONFIG_ARCH_OMAP2PLUS
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index ac5bc8857a51456efb3fc32e620a8d9d24e1c426..e4db6b9a55c615a9ea611861801cf0f3ab433a09 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -139,6 +139,7 @@ static void __init omap_clk_register_apll(void *user,
struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *ad = clk_hw->dpll_data;
+ const char *name;
struct clk *clk;
const struct clk_init_data *init = clk_hw->hw.init;
@@ -166,7 +167,8 @@ static void __init omap_clk_register_apll(void *user,
ad->clk_bypass = __clk_get_hw(clk);
- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
+ name = ti_dt_clk_name(node);
+ clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init->parent_names);
@@ -198,7 +200,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
clk_hw->dpll_data = ad;
clk_hw->hw.init = init;
- init->name = node->name;
+ init->name = ti_dt_clk_name(node);
init->ops = &apll_ck_ops;
init->num_parents = of_clk_get_parent_count(node);
@@ -347,6 +349,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
struct dpll_data *ad = NULL;
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
+ const char *name;
struct clk *clk;
const char *parent_name;
u32 val;
@@ -362,7 +365,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
clk_hw->dpll_data = ad;
clk_hw->hw.init = init;
init->ops = &omap2_apll_ops;
- init->name = node->name;
+ name = ti_dt_clk_name(node);
+ init->name = name;
clk_hw->ops = &omap2_apll_hwops;
init->num_parents = of_clk_get_parent_count(node);
@@ -403,7 +407,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
if (ret)
goto cleanup;
- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
+ name = ti_dt_clk_name(node);
+ clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init);
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index f6f8a409f148f284eb49a5e3d8a261c23d0df4bf..d6e5f1511ace89ea98dcbc68092a19f2d15691f3 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -205,7 +205,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
return -ENOMEM;
clk->shift = shift;
- clk->name = node->name;
+ clk->name = ti_dt_clk_name(node);
ret = ti_clk_get_reg_addr(node, 0, &clk->reg);
if (ret) {
kfree(clk);
diff --git a/drivers/clk/ti/clk-33xx-compat.c b/drivers/clk/ti/clk-33xx-compat.c
deleted file mode 100644
index 3e07f127912ae9d0c1bbdc05532f07cd6c62dfe9..0000000000000000000000000000000000000000
--- a/drivers/clk/ti/clk-33xx-compat.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * AM33XX Clock init
- *
- * Copyright (C) 2013 Texas Instruments, Inc
- * Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/ti.h>
-#include <dt-bindings/clock/am3.h>
-
-#include "clock.h"
-
-static const char * const am3_gpio1_dbclk_parents[] __initconst = {
- "l4_per_cm:clk:0138:0",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
- { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
- { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
- { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
- { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
- { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
- { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
- { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
- { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
- { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
- { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
- { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
- { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
- { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
- { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
- { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
- { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
- { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
- { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
- { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
- { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
- { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
- { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
- { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
- { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
- { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
- { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
- { 0 },
-};
-
-static const char * const am3_gpio0_dbclk_parents[] __initconst = {
- "gpio0_dbclk_mux_ck",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
- { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
- { 0 },
-};
-
-static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
- "sys_clkin_ck",
- NULL,
-};
-
-static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
- "l4_wkup_cm:clk:0010:19",
- "l4_wkup_cm:clk:0010:30",
- NULL,
-};
-
-static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
- "l4_wkup_cm:clk:0010:20",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
- .max_div = 64,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
- "l4_wkup_cm:clk:0010:22",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
- .max_div = 64,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const char * const am3_dbg_clka_ck_parents[] __initconst = {
- "dpll_core_m4_ck",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
- { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
- { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
- { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
- { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
- { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
- { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
- { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
- { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
- { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
- { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
- { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
- { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
- { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
- { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
- { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
- { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
- { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
- { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
- { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
- { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
- { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
- { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
- { 0 },
-};
-
-const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
- { 0x44e00014, am3_l4_per_clkctrl_regs },
- { 0x44e00404, am3_l4_wkup_clkctrl_regs },
- { 0x44e00604, am3_mpu_clkctrl_regs },
- { 0x44e00800, am3_l4_rtc_clkctrl_regs },
- { 0x44e00904, am3_gfx_l3_clkctrl_regs },
- { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
- { 0 },
-};
-
-struct ti_dt_clk am33xx_compat_clks[] = {
- DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
- DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
- DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
- DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
- DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
- DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
- DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
- DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
- DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
- DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
- DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
- DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
- { .node_name = NULL },
-};
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index f2c22120aaa75603e74a7dada30386ccf8b8ce4b..b4d142adede4f5c3fc0cceb9ae760bd153e8edee 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -279,10 +279,7 @@ int __init am33xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- ti_dt_clocks_register(am33xx_compat_clks);
- else
- ti_dt_clocks_register(am33xx_clks);
+ ti_dt_clocks_register(am33xx_clks);
omap2_clk_disable_autoidle_all();
diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c
deleted file mode 100644
index 5130398433921218f679059f1b78a750428e5393..0000000000000000000000000000000000000000
--- a/drivers/clk/ti/clk-43xx-compat.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * AM43XX Clock init
- *
- * Copyright (C) 2013 Texas Instruments, Inc
- * Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/ti.h>
-#include <dt-bindings/clock/am4.h>
-
-#include "clock.h"
-
-static const char * const am4_synctimer_32kclk_parents[] __initconst = {
- "mux_synctimer32k_ck",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
- { 0 },
-};
-
-static const char * const am4_gpio0_dbclk_parents[] __initconst = {
- "gpio0_dbclk_mux_ck",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
- { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
- { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
- { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
- { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
- { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
- { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
- { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
- { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
- { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
- { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
- { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
- { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
- { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
- { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
- { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
- { 0 },
-};
-
-static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
- "dpll_per_clkdcoldo",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
- { 0 },
-};
-
-static const char * const am4_gpio1_dbclk_parents[] __initconst = {
- "clkdiv32k_ick",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
- { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
- { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
- { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
- { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
- { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
- { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
- { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
- { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
- { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
- { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
- { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
- { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
- { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
- { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
- { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
- { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
- { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
- { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
- { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
- { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
- { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
- { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
- { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
- { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
- { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
- { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
- { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
- { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
- { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
- { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
- { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
- { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
- { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
- { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
- { 0 },
-};
-
-const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
- { 0x44df2820, am4_l4_wkup_clkctrl_regs },
- { 0x44df8320, am4_mpu_clkctrl_regs },
- { 0x44df8420, am4_gfx_l3_clkctrl_regs },
- { 0x44df8520, am4_l4_rtc_clkctrl_regs },
- { 0x44df8820, am4_l4_per_clkctrl_regs },
- { 0 },
-};
-
-const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
- { 0x44df2820, am4_l4_wkup_clkctrl_regs },
- { 0x44df8320, am4_mpu_clkctrl_regs },
- { 0x44df8420, am4_gfx_l3_clkctrl_regs },
- { 0x44df8820, am4_l4_per_clkctrl_regs },
- { 0 },
-};
-
-struct ti_dt_clk am43xx_compat_clks[] = {
- DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
- DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
- DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
- DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
- DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
- DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
- DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
- DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
- DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
- DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
- { .node_name = NULL },
-};
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 6e97a541cfd36f73e6467c7e793840021cb0f148..2ff4ff3d95d5d6f42dff51026ab9e7c36f7148b9 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -282,10 +282,7 @@ int __init am43xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- ti_dt_clocks_register(am43xx_compat_clks);
- else
- ti_dt_clocks_register(am43xx_clks);
+ ti_dt_clocks_register(am43xx_clks);
omap2_clk_disable_autoidle_all();
diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c
deleted file mode 100644
index ddf7c827794622423fc13eae82ba093402078316..0000000000000000000000000000000000000000
--- a/drivers/clk/ti/clk-7xx-compat.c
+++ /dev/null
@@ -1,820 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * DRA7 Clock init
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- *
- * Tero Kristo (t-kristo@ti.com)
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk/ti.h>
-#include <dt-bindings/clock/dra7.h>
-
-#include "clock.h"
-
-#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
-#define DRA7_DPLL_USB_DEFFREQ 960000000
-
-static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
- { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
- { 0 },
-};
-
-static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
- "per_abe_x1_gfclk2_div",
- "video1_clk2_div",
- "video2_clk2_div",
- "hdmi_clk2_div",
- NULL,
-};
-
-static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
- "abe_24m_fclk",
- "abe_sys_clk_div",
- "func_24m_clk",
- "atl_clkin3_ck",
- "atl_clkin2_ck",
- "atl_clkin1_ck",
- "atl_clkin0_ck",
- "sys_clkin2",
- "ref_clkin0_ck",
- "ref_clkin1_ck",
- "ref_clkin2_ck",
- "ref_clkin3_ck",
- "mlb_clk",
- "mlbp_clk",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
- "timer_sys_clk_div",
- "sys_32k_ck",
- "sys_clkin2",
- "ref_clkin0_ck",
- "ref_clkin1_ck",
- "ref_clkin2_ck",
- "ref_clkin3_ck",
- "abe_giclk_div",
- "video1_div_clk",
- "video2_div_clk",
- "hdmi_div_clk",
- "clkoutmux0_clk_mux",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
- "func_48m_fclk",
- "dpll_per_m2x2_ck",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
- { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
- { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
- { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
- { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
- { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
- { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
- { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
- { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
- { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
- { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
- { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
- { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
- { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { 0 },
-};
-
-static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
- "sys_32k_ck",
- "video1_clkin_ck",
- "video2_clkin_ck",
- "hdmi_clkin_ck",
- NULL,
-};
-
-static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
- "l3_iclk_div",
- "dpll_abe_m2_ck",
- "atl_cm:clk:0000:24",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
- { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
- { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
- { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
- { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
- { 0 },
-};
-
-static const char * const dra7_dss_dss_clk_parents[] __initconst = {
- "dpll_per_h12x2_ck",
- NULL,
-};
-
-static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
- "func_48m_fclk",
- NULL,
-};
-
-static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
- "hdmi_dpll_clk_mux",
- NULL,
-};
-
-static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
- "sys_32k_ck",
- NULL,
-};
-
-static const char * const dra7_dss_video1_clk_parents[] __initconst = {
- "video1_dpll_clk_mux",
- NULL,
-};
-
-static const char * const dra7_dss_video2_clk_parents[] __initconst = {
- "video2_dpll_clk_mux",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
- { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
- { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
- { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
- { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
- { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
- { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
- { 0 },
-};
-
-static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
- "func_128m_clk",
- "dpll_per_m2x2_ck",
- NULL,
-};
-
-static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
- "l3init_cm:clk:0008:24",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
- .max_div = 4,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
- { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
- { 0 },
-};
-
-static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
- "l3init_cm:clk:0010:24",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
- .max_div = 4,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
- { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
- { 0 },
-};
-
-static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
- "l3init_960m_gfclk",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_sata_ref_clk_parents[] __initconst = {
- "sys_clkin1",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
- "apll_pcie_ck",
- NULL,
-};
-
-static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
- "optfclk_pciephy_div",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
- { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
- { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
- "dpll_gmac_h11x2_ck",
- "rmii_clk_ck",
- NULL,
-};
-
-static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
- "video1_clkin_ck",
- "video2_clkin_ck",
- "dpll_abe_m2_ck",
- "hdmi_clkin_ck",
- "l3_iclk_div",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
- { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
- { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
- { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
- { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
- { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
- { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
- { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
- { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
- { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
- { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
- { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
- { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
- { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
- { 0 },
-};
-
-static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
- "timer_sys_clk_div",
- "sys_32k_ck",
- "sys_clkin2",
- "ref_clkin0_ck",
- "ref_clkin1_ck",
- "ref_clkin2_ck",
- "ref_clkin3_ck",
- "abe_giclk_div",
- "video1_div_clk",
- "video2_div_clk",
- "hdmi_div_clk",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
- "l4per_cm:clk:0120:24",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
- .max_div = 4,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
- { 0 },
-};
-
-static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
- "l4per_cm:clk:0128:24",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
- .max_div = 4,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
- "func_128m_clk",
- "dpll_per_h13x2_ck",
- NULL,
-};
-
-static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
- "l4per_cm:clk:0138:24",
- NULL,
-};
-
-static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
- .max_div = 4,
- .flags = CLK_DIVIDER_POWER_OF_TWO,
-};
-
-static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
- { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
- { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
- { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
- { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
- { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
- { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
- { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
- { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
- { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
- { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
- { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
- { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
- { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
- { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
- { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
- { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
- { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
- { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
- { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
- { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
- { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
- { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
- { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
- { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
- { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
- { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
- { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
- { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
- { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
- { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
- { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
- { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
- { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
- { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
- { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
- { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
- { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
- { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
- { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
- { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
- { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
- { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
- { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
- { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
- { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
- { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
- { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
- { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
- { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
- { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
- { 0 },
-};
-
-static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
- "sys_clkin1",
- "sys_clkin2",
- NULL,
-};
-
-static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
- { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
- { 0 },
-};
-
-static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
- { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
- { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
- { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
- { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
- { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
- { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
- { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
- { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
- { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
- { 0 },
-};
-
-const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = {
- { 0x4a005320, dra7_mpu_clkctrl_regs },
- { 0x4a005540, dra7_ipu_clkctrl_regs },
- { 0x4a005740, dra7_rtc_clkctrl_regs },
- { 0x4a008620, dra7_coreaon_clkctrl_regs },
- { 0x4a008720, dra7_l3main1_clkctrl_regs },
- { 0x4a008a20, dra7_dma_clkctrl_regs },
- { 0x4a008b20, dra7_emif_clkctrl_regs },
- { 0x4a008c00, dra7_atl_clkctrl_regs },
- { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
- { 0x4a008e20, dra7_l3instr_clkctrl_regs },
- { 0x4a009120, dra7_dss_clkctrl_regs },
- { 0x4a009320, dra7_l3init_clkctrl_regs },
- { 0x4a009700, dra7_l4per_clkctrl_regs },
- { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
- { 0 },
-};
-
-struct ti_dt_clk dra7xx_compat_clks[] = {
- DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
- DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
- DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
- DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
- DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
- DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
- DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
- DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
- DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
- DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
- DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
- DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
- DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
- DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
- DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
- DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
- DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
- DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
- DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
- DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
- DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
- DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
- DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
- DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
- DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
- DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
- DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
- DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
- DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
- DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
- DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
- DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
- DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
- DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
- DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
- DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
- DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
- DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
- DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
- DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
- DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
- DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
- DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
- DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
- DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
- DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
- DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
- DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
- DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
- DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
- DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
- DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
- DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
- DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
- DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
- DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
- DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
- DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
- DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
- DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
- DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
- DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
- DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
- DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
- DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
- DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
- DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
- DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
- DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
- DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
- DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
- DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
- DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
- DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
- DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
- DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
- DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
- DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
- DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
- DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
- DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
- DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
- DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
- DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
- DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
- DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
- { .node_name = NULL },
-};
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 8b9118ccd4cd1905742fed37b2743d2ce490c3c4..0f099441543f709a9476bb7987c77450806a5efd 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -946,10 +946,7 @@ int __init dra7xx_dt_clk_init(void)
int rc;
struct clk *dpll_ck, *hdcp_ck;
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- ti_dt_clocks_register(dra7xx_compat_clks);
- else
- ti_dt_clocks_register(dra7xx_clks);
+ ti_dt_clocks_register(dra7xx_clks);
omap2_clk_disable_autoidle_all();
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 8d4c08b034bdde50e77b60bd15cacba7860698b2..aa0950c4f4985423bef5cda1aca74474445c8b9d 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -173,6 +173,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
struct dra7_atl_desc *clk_hw = NULL;
struct clk_init_data init = { NULL };
const char **parent_names = NULL;
+ const char *name;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@@ -183,7 +184,8 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
clk_hw->hw.init = &init;
clk_hw->divider = 1;
- init.name = node->name;
+ name = ti_dt_clk_name(node);
+ init.name = name;
init.ops = &atl_clk_ops;
init.flags = CLK_IGNORE_UNUSED;
init.num_parents = of_clk_get_parent_count(node);
@@ -203,7 +205,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
init.parent_names = parent_names;
- clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
+ clk = ti_clk_register(NULL, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 3da33c786d77ce397db85ec185aa5f77530e321c..3463579220b51b15e1e6631d56b462fa35c674a2 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -119,19 +119,58 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
return 0;
}
+/*
+ * Eventually we could standardize to using '_' for clk-*.c files to follow the
+ * TRM naming and leave out the tmp name here.
+ */
+static struct device_node *ti_find_clock_provider(struct device_node *from,
+ const char *name)
+{
+ struct device_node *np;
+ bool found = false;
+ const char *n;
+ char *tmp;
+
+ tmp = kstrdup(name, GFP_KERNEL);
+ if (!tmp)
+ return NULL;
+ strreplace(tmp, '-', '_');
+
+ /* Node named "clock" with "clock-output-names" */
+ for_each_of_allnodes_from(from, np) {
+ if (of_property_read_string_index(np, "clock-output-names",
+ 0, &n))
+ continue;
+
+ if (!strncmp(n, tmp, strlen(tmp))) {
+ found = true;
+ break;
+ }
+ }
+ of_node_put(from);
+ kfree(tmp);
+
+ if (found)
+ return np;
+
+ /* Fall back to using old node name base provider name */
+ return of_find_node_by_name(from, name);
+}
+
/**
* ti_dt_clocks_register - register DT alias clocks during boot
* @oclks: list of clocks to register
*
* Register alias or non-standard DT clock entries during boot. By
- * default, DT clocks are found based on their node name. If any
+ * default, DT clocks are found based on their clock-output-names
+ * property, or the clock node name for legacy cases. If any
* additional con-id / dev-id -> clock mapping is required, use this
* function to list these.
*/
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
{
struct ti_dt_clk *c;
- struct device_node *node, *parent;
+ struct device_node *node, *parent, *child;
struct clk *clk;
struct of_phandle_args clkspec;
char buf[64];
@@ -168,13 +207,16 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
if (num_args && clkctrl_nodes_missing)
continue;
- node = of_find_node_by_name(NULL, buf);
+ node = ti_find_clock_provider(NULL, buf);
if (num_args && compat_mode) {
parent = node;
- node = of_get_child_by_name(parent, "clock");
- if (!node)
- node = of_get_child_by_name(parent, "clk");
- of_node_put(parent);
+ child = of_get_child_by_name(parent, "clock");
+ if (!child)
+ child = of_get_child_by_name(parent, "clk");
+ if (child) {
+ of_node_put(parent);
+ node = child;
+ }
}
clkspec.np = node;
@@ -271,6 +313,8 @@ int ti_clk_get_reg_addr(struct device_node *node, int index,
for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
if (clocks_node_ptr[i] == node->parent)
break;
+ if (clocks_node_ptr[i] == node->parent->parent)
+ break;
}
if (i == CLK_MAX_MEMMAPS) {
@@ -281,8 +325,12 @@ int ti_clk_get_reg_addr(struct device_node *node, int index,
reg->index = i;
if (of_property_read_u32_index(node, "reg", index, &val)) {
- pr_err("%pOFn must have reg[%d]!\n", node, index);
- return -EINVAL;
+ if (of_property_read_u32_index(node->parent, "reg",
+ index, &val)) {
+ pr_err("%pOFn or parent must have reg[%d]!\n",
+ node, index);
+ return -EINVAL;
+ }
}
reg->offset = val;
@@ -399,6 +447,24 @@ static const struct of_device_id simple_clk_match_table[] __initconst = {
{ }
};
+/**
+ * ti_dt_clk_name - init clock name from first output name or node name
+ * @np: device node
+ *
+ * Use the first clock-output-name for the clock name if found. Fall back
+ * to legacy naming based on node name.
+ */
+const char *ti_dt_clk_name(struct device_node *np)
+{
+ const char *name;
+
+ if (!of_property_read_string_index(np, "clock-output-names", 0,
+ &name))
+ return name;
+
+ return np->name;
+}
+
/**
* ti_clk_add_aliases - setup clock aliases
*
@@ -415,7 +481,7 @@ void __init ti_clk_add_aliases(void)
clkspec.np = np;
clk = of_clk_get_from_provider(&clkspec);
- ti_clk_add_alias(NULL, clk, np->name);
+ ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np));
}
}
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 864c484bde1b4d61b3d8acb7d7120fd1fb4604b7..064066e9e85b738d36209bef01c7161f7e447446 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -469,14 +469,32 @@ static void __init _clkctrl_add_provider(void *data,
of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
}
-/* Get clock name based on compatible string for clkctrl */
-static char * __init clkctrl_get_name(struct device_node *np)
+/*
+ * Get clock name based on "clock-output-names" property or the
+ * compatible property for clkctrl.
+ */
+static const char * __init clkctrl_get_name(struct device_node *np)
{
struct property *prop;
const int prefix_len = 11;
const char *compat;
+ const char *output;
char *name;
+ if (!of_property_read_string_index(np, "clock-output-names", 0,
+ &output)) {
+ const char *end;
+ int len;
+
+ len = strlen(output);
+ end = strstr(output, "_clkctrl");
+ if (end)
+ len -= strlen(end);
+ name = kstrndup(output, len, GFP_KERNEL);
+
+ return name;
+ }
+
of_property_for_each_string(np, "compatible", prop, compat) {
if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
/* Two letter minimum name length for l3, l4 etc */
@@ -505,7 +523,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
struct omap_clkctrl_clk *clkctrl_clk = NULL;
const __be32 *addrp;
bool legacy_naming;
- char *clkctrl_name;
+ const char *clkctrl_name;
u32 addr;
int ret;
char *c;
@@ -527,13 +545,8 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
data = omap5_clkctrl_data;
#endif
#ifdef CONFIG_SOC_DRA7XX
- if (of_machine_is_compatible("ti,dra7")) {
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- data = dra7_clkctrl_compat_data;
- else
- data = dra7_clkctrl_data;
- }
-
+ if (of_machine_is_compatible("ti,dra7"))
+ data = dra7_clkctrl_data;
if (of_machine_is_compatible("ti,dra72"))
soc_mask = CLKF_SOC_DRA72;
if (of_machine_is_compatible("ti,dra74"))
@@ -542,27 +555,15 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
soc_mask = CLKF_SOC_DRA76;
#endif
#ifdef CONFIG_SOC_AM33XX
- if (of_machine_is_compatible("ti,am33xx")) {
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- data = am3_clkctrl_compat_data;
- else
- data = am3_clkctrl_data;
- }
+ if (of_machine_is_compatible("ti,am33xx"))
+ data = am3_clkctrl_data;
#endif
#ifdef CONFIG_SOC_AM43XX
- if (of_machine_is_compatible("ti,am4372")) {
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- data = am4_clkctrl_compat_data;
- else
- data = am4_clkctrl_data;
- }
+ if (of_machine_is_compatible("ti,am4372"))
+ data = am4_clkctrl_data;
- if (of_machine_is_compatible("ti,am438x")) {
- if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
- data = am438x_clkctrl_compat_data;
- else
- data = am438x_clkctrl_data;
- }
+ if (of_machine_is_compatible("ti,am438x"))
+ data = am438x_clkctrl_data;
#endif
#ifdef CONFIG_SOC_TI81XX
if (of_machine_is_compatible("ti,dm814"))
@@ -603,7 +604,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
/*
* The code below can be removed when all clkctrl nodes use domain
- * specific compatible proprerty and standard clock node naming
+ * specific compatible property and standard clock node naming
*/
if (legacy_naming) {
provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index f1dd62de2bfcb64e7367b6c8252cee43cbdb81c8..c841d2d28111592e9109b7f8ba1db4c0cba60e84 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -201,10 +201,7 @@ extern const struct omap_clkctrl_data am3_clkctrl_data[];
extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
extern struct ti_dt_clk am33xx_compat_clks[];
extern const struct omap_clkctrl_data am4_clkctrl_data[];
-extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
-extern struct ti_dt_clk am43xx_compat_clks[];
extern const struct omap_clkctrl_data am438x_clkctrl_data[];
-extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
extern const struct omap_clkctrl_data dm814_clkctrl_data[];
extern const struct omap_clkctrl_data dm816_clkctrl_data[];
@@ -214,6 +211,7 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
const char *con);
struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
const char *con);
+const char *ti_dt_clk_name(struct device_node *np);
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
void ti_clk_add_aliases(void);
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index 74831b2752b3b432220d658a13ff60179a84d408..24179c907774ae03b45df059276822c80366c1d7 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -131,7 +131,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
{
struct clk *clk;
struct clk_hw *clk_hw;
- const char *clkdm_name = node->name;
+ const char *clkdm_name = ti_dt_clk_name(node);
int i;
unsigned int num_clks;
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index eaa43575cfa5e743737dfa538a33163f9fa4a8a9..8d60319be3683c8e9c86052d4590474eaa095c6c 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -125,6 +125,7 @@ static void __init _register_composite(void *user,
struct component_clk *comp;
int num_parents = 0;
const char **parent_names = NULL;
+ const char *name;
int i;
int ret;
@@ -172,7 +173,8 @@ static void __init _register_composite(void *user,
goto cleanup;
}
- clk = clk_register_composite(NULL, node->name,
+ name = ti_dt_clk_name(node);
+ clk = clk_register_composite(NULL, name,
parent_names, num_parents,
_get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
&ti_clk_mux_ops,
@@ -182,7 +184,7 @@ static void __init _register_composite(void *user,
&ti_composite_gate_ops, 0);
if (!IS_ERR(clk)) {
- ret = ti_clk_add_alias(NULL, clk, node->name);
+ ret = ti_clk_add_alias(NULL, clk, name);
if (ret) {
clk_unregister(clk);
goto cleanup;
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 28080df92f7226a6e61d6f2f2077c9370d95afcd..9fbea0997b43292b3fea0dde6fb938e56562ff40 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -320,10 +320,12 @@ static struct clk *_register_divider(struct device_node *node,
struct clk *clk;
struct clk_init_data init;
const char *parent_name;
+ const char *name;
parent_name = of_clk_get_parent_name(node, 0);
- init.name = node->name;
+ name = ti_dt_clk_name(node);
+ init.name = name;
init.ops = &ti_clk_divider_ops;
init.flags = flags;
init.parent_names = (parent_name ? &parent_name : NULL);
@@ -332,7 +334,7 @@ static struct clk *_register_divider(struct device_node *node,
div->hw.init = &init;
/* register the clock */
- clk = ti_clk_register(NULL, &div->hw, node->name);
+ clk = ti_clk_register(NULL, &div->hw, name);
if (IS_ERR(clk))
kfree(div);
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index e9f9aee936ae8e722a7f81b8c06f1eb98f3642fd..7c6dc8449b22f5422ce03fb7672741ce87800593 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -164,6 +164,7 @@ static void __init _register_dpll(void *user,
struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *dd = clk_hw->dpll_data;
+ const char *name;
struct clk *clk;
const struct clk_init_data *init = hw->init;
@@ -193,7 +194,8 @@ static void __init _register_dpll(void *user,
dd->clk_bypass = __clk_get_hw(clk);
/* register the clock */
- clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
+ name = ti_dt_clk_name(node);
+ clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -227,7 +229,7 @@ static void _register_dpll_x2(struct device_node *node,
struct clk *clk;
struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw;
- const char *name = node->name;
+ const char *name = ti_dt_clk_name(node);
const char *parent_name;
parent_name = of_clk_get_parent_name(node, 0);
@@ -304,7 +306,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = init;
- init->name = node->name;
+ init->name = ti_dt_clk_name(node);
init->ops = ops;
init->num_parents = of_clk_get_parent_count(node);
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 8024c6d2b9e95c5119d493bca10195c9b334be30..749c6b73abff3991e91254f32d77ecb4d279e0f6 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -19,6 +19,8 @@
#include <linux/of_address.h>
#include <linux/clk/ti.h>
+#include "clock.h"
+
/* FAPLL Control Register PLL_CTRL */
#define FAPLL_MAIN_MULT_N_SHIFT 16
#define FAPLL_MAIN_DIV_P_SHIFT 8
@@ -542,6 +544,7 @@ static void __init ti_fapll_setup(struct device_node *node)
struct clk_init_data *init = NULL;
const char *parent_name[2];
struct clk *pll_clk;
+ const char *name;
int i;
fd = kzalloc(sizeof(*fd), GFP_KERNEL);
@@ -559,7 +562,8 @@ static void __init ti_fapll_setup(struct device_node *node)
goto free;
init->ops = &ti_fapll_ops;
- init->name = node->name;
+ name = ti_dt_clk_name(node);
+ init->name = name;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 2) {
@@ -591,7 +595,7 @@ static void __init ti_fapll_setup(struct device_node *node)
if (fapll_is_ddr_pll(fd->base))
fd->bypass_bit_inverted = true;
- fd->name = node->name;
+ fd->name = name;
fd->hw.init = init;
/* Register the parent PLL */
@@ -638,8 +642,7 @@ static void __init ti_fapll_setup(struct device_node *node)
freq = NULL;
}
synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
- output_name, node->name,
- pll_clk);
+ output_name, name, pll_clk);
if (IS_ERR(synth_clk))
continue;
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
index 7cbe896db07166532886c9b7613acc79f3efa068..8cb00d0af966205015490ec9d794adbe49bebb36 100644
--- a/drivers/clk/ti/fixed-factor.c
+++ b/drivers/clk/ti/fixed-factor.c
@@ -36,7 +36,7 @@
static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
{
struct clk *clk;
- const char *clk_name = node->name;
+ const char *clk_name = ti_dt_clk_name(node);
const char *parent_name;
u32 div, mult;
u32 flags = 0;
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index b1d0fdb40a75a0382db4ce1d0cf073953f720ad9..0033de9beb4cd1875427a7e602eef9e4449f3ee2 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -138,6 +138,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
struct clk *clk;
const char *parent_name;
struct clk_omap_reg reg;
+ const char *name;
u8 enable_bit = 0;
u32 val;
u32 flags = 0;
@@ -164,7 +165,8 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
clk_gate_flags |= INVERT_ENABLE;
- clk = _register_gate(NULL, node->name, parent_name, flags, ®,
+ name = ti_dt_clk_name(node);
+ clk = _register_gate(NULL, name, parent_name, flags, ®,
enable_bit, clk_gate_flags, ops, hw_ops);
if (!IS_ERR(clk))
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 83e34429d3b10b627a31f979b9bd31627bebdcd8..dd2b455183a91d6e9770bc73d1fb956115cd6535 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -72,6 +72,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
const char *parent_name;
struct clk_omap_reg reg;
u8 enable_bit = 0;
+ const char *name;
u32 val;
if (ti_clk_get_reg_addr(node, 0, ®))
@@ -86,7 +87,8 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
return;
}
- clk = _register_interface(NULL, node->name, parent_name, ®,
+ name = ti_dt_clk_name(node);
+ clk = _register_interface(NULL, name, parent_name, ®,
enable_bit, ops);
if (!IS_ERR(clk))
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 0069e7cf3ebcc375935078b2412040cda6d11819..15de513d2d818bc99c4d46f78772884eb4fbb3a9 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -176,6 +176,7 @@ static void of_mux_clk_setup(struct device_node *node)
struct clk_omap_reg reg;
unsigned int num_parents;
const char **parent_names;
+ const char *name;
u8 clk_mux_flags = 0;
u32 mask = 0;
u32 shift = 0;
@@ -213,7 +214,8 @@ static void of_mux_clk_setup(struct device_node *node)
mask = (1 << fls(mask)) - 1;
- clk = _register_mux(NULL, node->name, parent_names, num_parents,
+ name = ti_dt_clk_name(node);
+ clk = _register_mux(NULL, name, parent_names, num_parents,
flags, ®, shift, mask, latch, clk_mux_flags,
NULL);
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 204b83d911b902865fbd130d31a48512ea5a1ca8..7bdeaff2bfd68b00a25e6cd9ef4f0623a8b2cc9a 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -349,19 +349,20 @@ static void __init zynq_clk_setup(struct device_node *np)
/* Peripheral clocks */
for (i = fclk0; i <= fclk3; i++) {
int enable = !!(fclk_enable & BIT(i - fclk0));
+
zynq_clk_register_fclk(i, clk_output_name[i],
SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
periph_parents, enable);
}
- zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
- SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+ zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL,
+ SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
- zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
- SLCR_SMC_CLK_CTRL, periph_parents, 0);
+ zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL,
+ SLCR_SMC_CLK_CTRL, periph_parents, 0);
- zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
- SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+ zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL,
+ SLCR_PCAP_CLK_CTRL, periph_parents, 0);
zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
index 89495154127673c7043b9d26ab8b7841769b5935..dfbad5c87933c202bc0012c31b2d44916e87ca0f 100644
--- a/include/dt-bindings/clock/am3.h
+++ b/include/dt-bindings/clock/am3.h
@@ -8,99 +8,6 @@
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
-
-/* l4_per clocks */
-#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
-#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
-#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
-#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
-#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
-#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
-#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
-#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
-#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
-#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
-#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
-#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
-#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
-#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
-#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
-#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
-#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
-#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
-#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
-#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
-#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
-#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
-#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
-#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
-#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
-#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
-#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
-#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
-#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
-#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
-#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
-#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
-#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
-#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
-#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
-#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
-#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
-#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
-#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
-#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
-#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
-#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
-#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
-#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
-#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
-#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
-#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
-#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
-#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
-#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
-#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
-#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
-#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
-
-/* l4_wkup clocks */
-#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
-#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
-#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
-#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
-#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
-#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
-#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
-#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
-#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
-#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
-#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
-#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
-#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
-#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
-
-/* mpu clocks */
-#define AM3_MPU_CLKCTRL_OFFSET 0x4
-#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
-#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
-
-/* l4_rtc clocks */
-#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
-
-/* gfx_l3 clocks */
-#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
-#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
-#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
-
-/* l4_cefuse clocks */
-#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
-#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
-#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
-
-/* XXX: Compatibility part end */
-
/* l4ls clocks */
#define AM3_L4LS_CLKCTRL_OFFSET 0x38
#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h
index 4be6c5961f342abb3b4b39aaa929dce18985f796..a65b082e9cff4eaa7f68ab28bd4af16d3f310ca2 100644
--- a/include/dt-bindings/clock/am4.h
+++ b/include/dt-bindings/clock/am4.h
@@ -8,104 +8,6 @@
#define AM4_CLKCTRL_OFFSET 0x20
#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
-
-/* l4_wkup clocks */
-#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
-#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
-#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
-#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
-#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
-#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
-#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
-#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
-#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
-#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
-#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
-#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
-
-/* mpu clocks */
-#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
-
-/* gfx_l3 clocks */
-#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
-
-/* l4_rtc clocks */
-#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
-
-/* l4_per clocks */
-#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
-#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
-#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
-#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
-#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
-#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
-#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
-#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
-#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
-#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
-#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
-#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
-#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
-#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
-#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
-#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
-#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
-#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
-#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
-#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
-#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
-#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
-#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
-#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
-#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
-#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
-#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
-#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
-#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
-#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
-#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
-#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
-#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
-#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
-#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
-#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
-#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
-#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
-#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
-#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
-#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
-#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
-#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
-#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
-#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
-#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
-#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
-#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
-#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
-#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
-#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
-#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
-#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
-#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
-#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
-#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
-#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
-#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
-#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
-#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
-#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
-#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
-#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
-#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
-#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
-#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
-#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
-#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
-#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
-
-/* XXX: Compatibility part end. */
-
/* l3s_tsc clocks */
#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index 29ff6b89584874929137031b2ec28a778b14399b..8a903c78c5a545efb1ae0d10f5ca81745887c60e 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -8,174 +8,6 @@
#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
-/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
-
-/* mpu clocks */
-#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-
-/* ipu clocks */
-#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
-#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
-#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
-#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
-#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
-#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
-#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
-#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
-#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
-
-/* rtc clocks */
-#define DRA7_RTC_CLKCTRL_OFFSET 0x40
-#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
-#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
-
-/* vip clocks */
-#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
-#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
-
-/* vpe clocks */
-#define DRA7_VPE_CLKCTRL_OFFSET 0x60
-#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
-#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
-
-/* coreaon clocks */
-#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
-#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
-
-/* l3main1 clocks */
-#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
-#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
-#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
-#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
-#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
-#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
-
-/* dma clocks */
-#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-
-/* emif clocks */
-#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-
-/* atl clocks */
-#define DRA7_ATL_CLKCTRL_OFFSET 0x0
-#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
-#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
-
-/* l4cfg clocks */
-#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
-#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
-#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
-#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
-#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
-#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
-#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
-#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
-#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
-#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
-#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
-#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
-#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
-#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
-
-/* l3instr clocks */
-#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
-
-/* dss clocks */
-#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
-
-/* l3init clocks */
-#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
-#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
-#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
-#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
-#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
-#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
-#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
-#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
-#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
-#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
-#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
-#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
-
-/* l4per clocks */
-#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
-#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
-#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
-#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
-#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
-#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
-#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
-#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
-#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
-#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
-#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
-#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
-#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
-#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
-#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
-#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
-#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
-#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
-#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
-#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
-#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
-#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
-#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
-#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
-#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
-#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
-#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
-#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
-#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
-#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
-#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
-#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
-#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
-#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
-#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
-#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
-#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
-#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
-#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
-#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
-#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
-#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
-#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
-#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
-#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
-#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
-#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
-#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
-#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
-#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
-#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
-#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
-#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
-#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
-#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
-#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
-#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
-#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
-#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
-
-/* wkupaon clocks */
-#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
-#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
-#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
-#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
-#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
-#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
-#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
-#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
-#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
-
-/* XXX: Compatibility part end. */
-
/* mpu clocks */
#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
diff --git a/include/dt-bindings/clock/starfive-jh7100-audio.h b/include/dt-bindings/clock/starfive-jh7100-audio.h
new file mode 100644
index 0000000000000000000000000000000000000000..fbb4eae6572bfc90301a7e1707aea41f6ab86636
--- /dev/null
+++ b/include/dt-bindings/clock/starfive-jh7100-audio.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__
+
+#define JH7100_AUDCLK_ADC_MCLK 0
+#define JH7100_AUDCLK_I2S1_MCLK 1
+#define JH7100_AUDCLK_I2SADC_APB 2
+#define JH7100_AUDCLK_I2SADC_BCLK 3
+#define JH7100_AUDCLK_I2SADC_BCLK_N 4
+#define JH7100_AUDCLK_I2SADC_LRCLK 5
+#define JH7100_AUDCLK_PDM_APB 6
+#define JH7100_AUDCLK_PDM_MCLK 7
+#define JH7100_AUDCLK_I2SVAD_APB 8
+#define JH7100_AUDCLK_SPDIF 9
+#define JH7100_AUDCLK_SPDIF_APB 10
+#define JH7100_AUDCLK_PWMDAC_APB 11
+#define JH7100_AUDCLK_DAC_MCLK 12
+#define JH7100_AUDCLK_I2SDAC_APB 13
+#define JH7100_AUDCLK_I2SDAC_BCLK 14
+#define JH7100_AUDCLK_I2SDAC_BCLK_N 15
+#define JH7100_AUDCLK_I2SDAC_LRCLK 16
+#define JH7100_AUDCLK_I2S1_APB 17
+#define JH7100_AUDCLK_I2S1_BCLK 18
+#define JH7100_AUDCLK_I2S1_BCLK_N 19
+#define JH7100_AUDCLK_I2S1_LRCLK 20
+#define JH7100_AUDCLK_I2SDAC16K_APB 21
+#define JH7100_AUDCLK_APB0_BUS 22
+#define JH7100_AUDCLK_DMA1P_AHB 23
+#define JH7100_AUDCLK_USB_APB 24
+#define JH7100_AUDCLK_USB_LPM 25
+#define JH7100_AUDCLK_USB_STB 26
+#define JH7100_AUDCLK_APB_EN 27
+#define JH7100_AUDCLK_VAD_MEM 28
+
+#define JH7100_AUDCLK_END 29
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_AUDIO_H__ */