From 62462a525b49e5b3096895b28a217fd3ec0b3caa Mon Sep 17 00:00:00 2001
From: Neal Liu <neal_liu@aspeedtech.com>
Date: Wed, 4 Jan 2023 09:34:34 +0800
Subject: [PATCH] ARM: dts: aspeed: Add ACRY/AHBC device controller node
Add acry & ahbc node to device tree for AST2600.
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index cc2f8b785917a..8246a60de0d08 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -98,6 +98,11 @@ gic: interrupt-controller@40461000 {
<0x40466000 0x2000>;
};
+ ahbc: bus@1e600000 {
+ compatible = "aspeed,ast2600-ahbc", "syscon";
+ reg = <0x1e600000 0x100>;
+ };
+
fmc: spi@1e620000 {
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
@@ -431,6 +436,14 @@ sbc: secure-boot-controller@1e6f2000 {
reg = <0x1e6f2000 0x1000>;
};
+ acry: crypto@1e6fa000 {
+ compatible = "aspeed,ast2600-acry";
+ reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
+ aspeed,ahbc = <&ahbc>;
+ };
+
video: video@1e700000 {
compatible = "aspeed,ast2600-video-engine";
reg = <0x1e700000 0x1000>;
--
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