From 908ca2dbc819f47ab3ef4d38f83e9e81c218b10d Mon Sep 17 00:00:00 2001
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Fri, 16 Oct 2015 15:42:28 -0700
Subject: [PATCH] ARM: dt: fpga: Added binding docs for Xilinx Zynq FPGA
manager.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
.../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
new file mode 100644
index 0000000000000..7018aa8968359
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
@@ -0,0 +1,19 @@
+Xilinx Zynq FPGA Manager
+
+Required properties:
+- compatible: should contain "xlnx,zynq-devcfg-1.0"
+- reg: base address and size for memory mapped io
+- interrupts: interrupt for the FPGA manager device
+- clocks: phandle for clocks required operation
+- clock-names: name for the clock, should be "ref_clk"
+- syscon: phandle for access to SLCR registers
+
+Example:
+ devcfg: devcfg@f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ interrupts = <0 8 4>;
+ clocks = <&clkc 12>;
+ clock-names = "ref_clk";
+ syscon = <&slcr>;
+ };
--
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