From a2e4b5adfdf85d4a94af8a7a9f44e3ee254fd77e Mon Sep 17 00:00:00 2001 From: Michael Walle <michael@walle.cc> Date: Fri, 18 Mar 2022 21:13:22 +0100 Subject: [PATCH] dt-bindings: net: mscc-miim: add lan966x compatible The MDIO controller has support to release the internal PHYs from reset by specifying a second memory resource. This is different between the currently supported SparX-5 and the LAN966x. Add a new compatible to distinguish between these two. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org> --- Documentation/devicetree/bindings/net/mscc-miim.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt index 7104679cf59d5..70e0cb1ee4853 100644 --- a/Documentation/devicetree/bindings/net/mscc-miim.txt +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO ================================================= Properties: -- compatible: must be "mscc,ocelot-miim" +- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim" - reg: The base address of the MDIO bus controller register bank. Optionally, a second register bank can be defined if there is an associated reset register for internal PHYs -- GitLab