diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 52c80c2a57f208924fb312a1ca1d03f02c4ea57b..600eef3f3ac7db71dc165946e657da08ee79a9ac 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -351,7 +351,7 @@ config SGI_IP27
select ARC64
select BOOT_ELF64
select DEFAULT_SGI_PARTITION
- select DMA_IP27
+ select DMA_COHERENT
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
select NR_CPUS_DEFAULT_64
@@ -761,9 +761,6 @@ config CFE
config DMA_COHERENT
bool
-config DMA_IP27
- bool
-
config DMA_NONCOHERENT
bool
select DMA_NEED_PCI_MAP_STATE
@@ -1368,7 +1365,7 @@ config CPU_SUPPORTS_64BIT_KERNEL
#
config HARDWARE_WATCHPOINTS
bool
- default y if CPU_MIPS32 || CPU_MIPS64
+ default y if CPU_MIPSR1 || CPU_MIPSR2
menu "Kernel type"
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 32880146cbc1dc4aa2361785e5d9c88bf23a77ae..6fd441d16af57e6af53fa410fee70dac5204d66c 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
.irq = AU1000_RTC_MATCH2_INT,
.set_next_event = au1x_rtcmatch2_set_next_event,
.set_mode = au1x_rtcmatch2_set_mode,
- .cpumask = CPU_MASK_ALL,
+ .cpumask = CPU_MASK_ALL_PTR,
};
static struct irqaction au1x_rtcmatch2_irqaction = {
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index e085feddb4a489b0f0220e6f0ea9882d970e5dde..5f4e49ba4713fcc1fdd3040074e04acd24cf255e 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -15,13 +15,11 @@
#include <linux/serial.h>
#include <linux/types.h>
#include <linux/string.h> /* for memset */
-#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/time.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
-#include <linux/string.h>
#include <asm/processor.h>
#include <asm/reboot.h>
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 34ea319be94c13cc08384b64b2535b46f119770f..f2baea3039bb8bfe6f95cc9828ff5dd0686b9510 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -53,7 +53,7 @@ CONFIG_GENERIC_TIME=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_ARC=y
-CONFIG_DMA_IP27=y
+CONFIG_DMA_COHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
# CONFIG_NO_IOPORT is not set
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index c996c3b4d074ddc2c3ed785b7bd9839e4c1cb663..1b332e15ab528522c19e4769c7691435e843dce1 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -50,7 +50,7 @@
static __inline__ void atomic_add(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -95,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
static __inline__ void atomic_sub(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -107,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -135,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
*/
static __inline__ int atomic_add_return(int i, atomic_t * v)
{
- unsigned long result;
+ int result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -154,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -187,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
static __inline__ int atomic_sub_return(int i, atomic_t * v)
{
- unsigned long result;
+ int result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -247,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
*/
static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
{
- unsigned long result;
+ int result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -270,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
- unsigned long temp;
+ int temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -429,7 +429,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
static __inline__ void atomic64_add(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -441,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -474,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
static __inline__ void atomic64_sub(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -486,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -514,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
*/
static __inline__ long atomic64_add_return(long i, atomic64_t * v)
{
- unsigned long result;
+ long result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -533,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -566,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
{
- unsigned long result;
+ long result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -585,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -626,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
*/
static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
{
- unsigned long result;
+ long result;
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
@@ -649,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
- unsigned long temp;
+ long temp;
__asm__ __volatile__(
" .set mips3 \n"
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index b5cf6457305a5812bf4a973a03453a6bc53b0527..3cb50d17b62d8062fbbabab24046673c6e183409 100644
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -80,11 +80,8 @@ struct rb532_gpio_reg {
/* Compact Flash GPIO pin */
#define CF_GPIO_NUM 13
-extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
-extern unsigned get_434_reg(unsigned reg_offs);
-extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
-extern unsigned char get_latch_u5(void);
extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
extern void rb532_gpio_set_istat(int bit, unsigned gpio);
+extern void rb532_gpio_set_func(unsigned gpio);
#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
index 56738d8ec4e2b46b7e9c864ff99c48529028f28a..023a5b100ed05d617f24fb2c11fa749384c571bf 100644
--- a/arch/mips/include/asm/mach-rc32434/irq.h
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -30,4 +30,7 @@
#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
+#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE
+#define GPIO_MAPPED_IRQ_GROUP 4
+
#endif /* __ASM_RC32434_IRQ_H */
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index f25a8491670329ec0298e97bb8685bea31a7a02b..6dc5f8df1f3e025f22ac893d44b76a25f0da0d8e 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -83,4 +83,7 @@ struct mpmc_device {
void __iomem *base;
};
+extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
+extern unsigned char get_latch_u5(void);
+
#endif /* __ASM_RC32434_RB_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 1f30d16d46697dcccdd4188524f4eaae91a6c5a9..ce47118e52b70e7265dab3caa00c84f2542cfafb 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -105,7 +105,7 @@ struct pt_watch_regs {
enum pt_watch_style style;
union {
struct mips32_watch_regs mips32;
- struct mips32_watch_regs mips64;
+ struct mips64_watch_regs mips64;
};
};
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
index a275661fa7e1da92bce69be7ee876329c691b1d7..8f77f774a2a01e3b70fee2bae89a1b036c89fc6f 100644
--- a/arch/mips/include/asm/termios.h
+++ b/arch/mips/include/asm/termios.h
@@ -9,6 +9,7 @@
#ifndef _ASM_TERMIOS_H
#define _ASM_TERMIOS_H
+#include <linux/errno.h>
#include <asm/termbits.h>
#include <asm/ioctls.h>
@@ -94,38 +95,81 @@ struct termio {
/*
* Translate a "termio" structure into a "termios". Ugh.
*/
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- unsigned short tmp; \
- get_user(tmp, &(termio)->c_iflag); \
- (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
- get_user(tmp, &(termio)->c_oflag); \
- (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
- get_user(tmp, &(termio)->c_cflag); \
- (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
- get_user(tmp, &(termio)->c_lflag); \
- (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
- get_user((termios)->c_line, &(termio)->c_line); \
- copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
+static inline int user_termio_to_kernel_termios(struct ktermios *termios,
+ struct termio __user *termio)
+{
+ unsigned short iflag, oflag, cflag, lflag;
+ unsigned int err;
+
+ if (!access_ok(VERIFY_READ, termio, sizeof(struct termio)))
+ return -EFAULT;
+
+ err = __get_user(iflag, &termio->c_iflag);
+ termios->c_iflag = (termios->c_iflag & 0xffff0000) | iflag;
+ err |=__get_user(oflag, &termio->c_oflag);
+ termios->c_oflag = (termios->c_oflag & 0xffff0000) | oflag;
+ err |=__get_user(cflag, &termio->c_cflag);
+ termios->c_cflag = (termios->c_cflag & 0xffff0000) | cflag;
+ err |=__get_user(lflag, &termio->c_lflag);
+ termios->c_lflag = (termios->c_lflag & 0xffff0000) | lflag;
+ err |=__get_user(termios->c_line, &termio->c_line);
+ if (err)
+ return -EFAULT;
+
+ if (__copy_from_user(termios->c_cc, termio->c_cc, NCC))
+ return -EFAULT;
+
+ return 0;
+}
/*
* Translate a "termios" structure into a "termio". Ugh.
*/
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- put_user((termios)->c_iflag, &(termio)->c_iflag); \
- put_user((termios)->c_oflag, &(termio)->c_oflag); \
- put_user((termios)->c_cflag, &(termio)->c_cflag); \
- put_user((termios)->c_lflag, &(termio)->c_lflag); \
- put_user((termios)->c_line, &(termio)->c_line); \
- copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
+static inline int kernel_termios_to_user_termio(struct termio __user *termio,
+ struct ktermios *termios)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, termio, sizeof(struct termio)))
+ return -EFAULT;
+
+ err = __put_user(termios->c_iflag, &termio->c_iflag);
+ err |= __put_user(termios->c_oflag, &termio->c_oflag);
+ err |= __put_user(termios->c_cflag, &termio->c_cflag);
+ err |= __put_user(termios->c_lflag, &termio->c_lflag);
+ err |= __put_user(termios->c_line, &termio->c_line);
+ if (err)
+ return -EFAULT;
+
+ if (__copy_to_user(termio->c_cc, termios->c_cc, NCC))
+ return -EFAULT;
+
+ return 0;
+}
+
+static inline int user_termios_to_kernel_termios(struct ktermios __user *k,
+ struct termios2 *u)
+{
+ return copy_from_user(k, u, sizeof(struct termios2)) ? -EFAULT : 0;
+}
+
+static inline int kernel_termios_to_user_termios(struct termios2 __user *u,
+ struct ktermios *k)
+{
+ return copy_to_user(u, k, sizeof(struct termios2)) ? -EFAULT : 0;
+}
+
+static inline int user_termios_to_kernel_termios_1(struct ktermios *k,
+ struct termios __user *u)
+{
+ return copy_from_user(k, u, sizeof(struct termios)) ? -EFAULT : 0;
+}
+
+static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
+ struct ktermios *k)
+{
+ return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0;
+}
#endif /* defined(__KERNEL__) */
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index 88badb42301066dd22ac9ce4164875cabaadf5cd..964ef7ede2684eaff7d8f8c1ad1e5e83a7b6c651 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -541,5 +541,6 @@ void tx4939_irq_init(void);
int tx4939_irq(void);
void tx4939_mtd_init(int ch);
void tx4939_ata_init(void);
+void tx4939_rtc_init(void);
#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index fb6f73148df2f7c7459648ed110fcdde62145f2a..8882e5766f27ce5b7a8a57932b4b103b7a69eaa7 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -458,7 +458,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
BUILD_HANDLER fpe fpe fpe silent /* #15 */
BUILD_HANDLER mdmx mdmx sti silent /* #22 */
#ifdef CONFIG_HARDWARE_WATCHPOINTS
- BUILD_HANDLER watch watch sti silent /* #23 */
+ /*
+ * For watch, interrupts will be enabled after the watch
+ * registers are read.
+ */
+ BUILD_HANDLER watch watch cli silent /* #23 */
#else
BUILD_HANDLER watch watch sti verbose /* #23 */
#endif
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index 5e77a3a21f98e7926cc789915ad65bbe64911a1a..42461310b185c683b9738fda5af742a74718b5ae 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -79,7 +79,8 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
euid = current_euid();
retval = -EPERM;
- if (euid != p->euid && euid != p->uid && !capable(CAP_SYS_NICE)) {
+ if (euid != p->cred->euid && euid != p->cred->uid &&
+ !capable(CAP_SYS_NICE)) {
read_unlock(&tasklist_lock);
goto out_unlock;
}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f6083c6bfaa4f3b411b06103a3e48936933ee3b9..b2d7041341b8f5afa3e313302c21b90e34e5ea3d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -944,6 +944,9 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
force_sig(SIGILL, current);
}
+/*
+ * Called with interrupts disabled.
+ */
asmlinkage void do_watch(struct pt_regs *regs)
{
u32 cause;
@@ -963,9 +966,12 @@ asmlinkage void do_watch(struct pt_regs *regs)
*/
if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
mips_read_watch_registers();
+ local_irq_enable();
force_sig(SIGTRAP, current);
- } else
+ } else {
mips_clear_watch_registers();
+ local_irq_enable();
+ }
}
asmlinkage void do_mcheck(struct pt_regs *regs)
@@ -1582,7 +1588,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size)
static char panic_null_cerr[] __cpuinitdata =
"Trying to set NULL cache error exception handler";
-/* Install uncached CPU exception handler */
+/*
+ * Install uncached CPU exception handler.
+ * This is suitable only for the cache error exception which is the only
+ * exception handler that is being run uncached.
+ */
void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
unsigned long size)
{
@@ -1593,7 +1603,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
unsigned long uncached_ebase = TO_UNCAC(ebase);
#endif
if (cpu_has_mips_r2)
- ebase += (read_c0_ebase() & 0x3ffff000);
+ uncached_ebase += (read_c0_ebase() & 0x3ffff000);
if (!addr)
panic(panic_null_cerr);
diff --git a/arch/mips/lib/memcpy-inatomic.S b/arch/mips/lib/memcpy-inatomic.S
index 736d0fb56a949772c546d85b32fc754c0177c499..68853a038d3fecf055daa4707af37c5462aa8cbe 100644
--- a/arch/mips/lib/memcpy-inatomic.S
+++ b/arch/mips/lib/memcpy-inatomic.S
@@ -21,7 +21,7 @@
* end of memory on some systems. It's also a seriously bad idea on non
* dma-coherent systems.
*/
-#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27)
+#ifdef CONFIG_DMA_NONCOHERENT
#undef CONFIG_CPU_HAS_PREFETCH
#endif
#ifdef CONFIG_MIPS_MALTA
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index c06cccf60becd10ddecd344ff940fe30d064c13f..56a1f85a1ce807504a95d54d49b3d3cab46b33a6 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -21,7 +21,7 @@
* end of memory on some systems. It's also a seriously bad idea on non
* dma-coherent systems.
*/
-#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27)
+#ifdef CONFIG_DMA_NONCOHERENT
#undef CONFIG_CPU_HAS_PREFETCH
#endif
#ifdef CONFIG_MIPS_MALTA
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6e99665ae860e540cafee642d5d3daf0c1537738..c43f4b26a69010b63154a734618060c0981b692e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -618,15 +618,35 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size)
r4k_blast_scache();
- else
+ else {
+ unsigned long lsize = cpu_scache_line_size();
+ unsigned long almask = ~(lsize - 1);
+
+ /*
+ * There is no clearly documented alignment requirement
+ * for the cache instruction on MIPS processors and
+ * some processors, among them the RM5200 and RM7000
+ * QED processors will throw an address error for cache
+ * hit ops with insufficient alignment. Solved by
+ * aligning the address to cache line size.
+ */
+ cache_op(Hit_Writeback_Inv_SD, addr & almask);
+ cache_op(Hit_Writeback_Inv_SD,
+ (addr + size - 1) & almask);
blast_inv_scache_range(addr, addr + size);
+ }
return;
}
if (cpu_has_safe_index_cacheops && size >= dcache_size) {
r4k_blast_dcache();
} else {
+ unsigned long lsize = cpu_dcache_line_size();
+ unsigned long almask = ~(lsize - 1);
+
R4600_HIT_CACHEOP_WAR_IMPL;
+ cache_op(Hit_Writeback_Inv_D, addr & almask);
+ cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask);
blast_inv_dcache_range(addr, addr + size);
}
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index fa636fc6b7b90403a2a8771ef3c5f023a1a82cd4..55767ad9f00ee4a5aec5be3e984d5a971b808eb9 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -97,7 +97,6 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
goto bad_area;
}
-survive:
/*
* If for any reason at all we couldn't handle the fault,
* make sure we exit gracefully rather than endlessly redo
@@ -167,21 +166,13 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
field, regs->regs[31]);
die("Oops", regs);
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
out_of_memory:
- up_read(&mm->mmap_sem);
- if (is_global_init(tsk)) {
- yield();
- down_read(&mm->mmap_sem);
- goto survive;
- }
- printk("VM: killing process %s\n", tsk->comm);
- if (user_mode(regs))
- do_group_exit(SIGKILL);
- goto no_context;
+ /*
+ * We ran out of memory, call the OOM killer, and return the userspace
+ * (which will retry the fault, or kill us if we got oom-killed).
+ */
+ pagefault_out_of_memory();
+ return;
do_sigbus:
up_read(&mm->mmap_sem);
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index 1c2821e2f494c303ccdee8b823ff5754fcb74abd..71f7d27b0d4cccf28dba3777b0a8848de53f82c4 100644
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -205,6 +205,8 @@ static int __init rc32434_pcibridge_init(void)
static int __init rc32434_pci_init(void)
{
+ void __iomem *io_map_base;
+
pr_info("PCI: Initializing PCI\n");
ioport_resource.start = rc32434_res_pci_io1.start;
@@ -212,6 +214,15 @@ static int __init rc32434_pci_init(void)
rc32434_pcibridge_init();
+ io_map_base = ioremap(rc32434_res_pci_io1.start,
+ rc32434_res_pci_io1.end - rc32434_res_pci_io1.start + 1);
+
+ if (!io_map_base)
+ return -ENOMEM;
+
+ rc32434_controller.io_map_base =
+ (unsigned long)io_map_base - rc32434_res_pci_io1.start;
+
register_pci_controller(&rc32434_controller);
rc32434_sync();
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index c1c29181bd4641de62977a19107a4d5ad64734c0..4a5f05b662aef219fbbc6dd28b8326b0f6b7c889 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -24,6 +24,7 @@
#include <linux/mtd/partitions.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
+#include <linux/serial_8250.h>
#include <asm/bootinfo.h>
@@ -39,6 +40,29 @@
#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
+extern unsigned int idt_cpu_freq;
+
+static struct mpmc_device dev3;
+
+void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev3.lock, flags);
+
+ dev3.state = (dev3.state | or_mask) & ~nand_mask;
+ writeb(dev3.state, dev3.base);
+
+ spin_unlock_irqrestore(&dev3.lock, flags);
+}
+EXPORT_SYMBOL(set_latch_u5);
+
+unsigned char get_latch_u5(void)
+{
+ return dev3.state;
+}
+EXPORT_SYMBOL(get_latch_u5);
+
static struct resource korina_dev0_res[] = {
{
.name = "korina_regs",
@@ -86,7 +110,7 @@ static struct korina_device korina_dev0_data = {
static struct platform_device korina_dev0 = {
.id = -1,
.name = "korina",
- .dev.platform_data = &korina_dev0_data,
+ .dev.driver_data = &korina_dev0_data,
.resource = korina_dev0_res,
.num_resources = ARRAY_SIZE(korina_dev0_res),
};
@@ -214,12 +238,32 @@ static struct platform_device rb532_wdt = {
.num_resources = ARRAY_SIZE(rb532_wdt_res),
};
+static struct plat_serial8250_port rb532_uart_res[] = {
+ {
+ .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
+ .irq = UART0_IRQ,
+ .regshift = 2,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF,
+ },
+ {
+ .flags = 0,
+ }
+};
+
+static struct platform_device rb532_uart = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev.platform_data = &rb532_uart_res,
+};
+
static struct platform_device *rb532_devs[] = {
&korina_dev0,
&nand_slot0,
&cf_slot0,
&rb532_led,
&rb532_button,
+ &rb532_uart,
&rb532_wdt
};
@@ -291,9 +335,20 @@ static int __init plat_setup_devices(void)
nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
+ /* Read and map device controller 3 */
+ dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
+
+ if (!dev3.base) {
+ printk(KERN_ERR "rb532: cannot remap device controller 3\n");
+ return -ENXIO;
+ }
+
/* Initialise the NAND device */
rb532_nand_setup();
+ /* set the uart clock to the current cpu frequency */
+ rb532_uart_res[0].uartclk = idt_cpu_freq;
+
return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
}
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 0e84c8ab6a3932b39adbfbe2cb8144fae39ba51d..37de05d595e725ebdc59513181d3f43709ce1cb4 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -41,8 +41,6 @@ struct rb532_gpio_chip {
void __iomem *regbase;
};
-struct mpmc_device dev3;
-
static struct resource rb532_gpio_reg0_res[] = {
{
.name = "gpio_reg0",
@@ -52,61 +50,6 @@ static struct resource rb532_gpio_reg0_res[] = {
}
};
-static struct resource rb532_dev3_ctl_res[] = {
- {
- .name = "dev3_ctl",
- .start = REGBASE + DEV3BASE,
- .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
- .flags = IORESOURCE_MEM,
- }
-};
-
-void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
-{
- unsigned long flags;
- unsigned data;
- unsigned i = 0;
-
- spin_lock_irqsave(&dev3.lock, flags);
-
- data = readl(IDT434_REG_BASE + reg_offs);
- for (i = 0; i != len; ++i) {
- if (val & (1 << i))
- data |= (1 << (i + bit));
- else
- data &= ~(1 << (i + bit));
- }
- writel(data, (IDT434_REG_BASE + reg_offs));
-
- spin_unlock_irqrestore(&dev3.lock, flags);
-}
-EXPORT_SYMBOL(set_434_reg);
-
-unsigned get_434_reg(unsigned reg_offs)
-{
- return readl(IDT434_REG_BASE + reg_offs);
-}
-EXPORT_SYMBOL(get_434_reg);
-
-void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&dev3.lock, flags);
-
- dev3.state = (dev3.state | or_mask) & ~nand_mask;
- writel(dev3.state, &dev3.base);
-
- spin_unlock_irqrestore(&dev3.lock, flags);
-}
-EXPORT_SYMBOL(set_latch_u5);
-
-unsigned char get_latch_u5(void)
-{
- return dev3.state;
-}
-EXPORT_SYMBOL(get_latch_u5);
-
/* rb532_set_bit - sanely set a bit
*
* bitval: new value for the bit
@@ -119,13 +62,11 @@ static inline void rb532_set_bit(unsigned bitval,
unsigned long flags;
u32 val;
- bitval = !!bitval; /* map parameter to {0,1} */
-
local_irq_save(flags);
val = readl(ioaddr);
- val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */
- val |= ( bitval << offset ); /* set bit if bitval == 1 */
+ val &= ~(!bitval << offset); /* unset bit if bitval == 0 */
+ val |= (!!bitval << offset); /* set bit if bitval == 1 */
writel(val, ioaddr);
local_irq_restore(flags);
@@ -171,8 +112,8 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
gpch = container_of(chip, struct rb532_gpio_chip, chip);
- if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
- return 1; /* alternate function, GPIOCFG is ignored */
+ /* disable alternate function in case it's set */
+ rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
return 0;
@@ -188,8 +129,8 @@ static int rb532_gpio_direction_output(struct gpio_chip *chip,
gpch = container_of(chip, struct rb532_gpio_chip, chip);
- if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
- return 1; /* alternate function, GPIOCFG is ignored */
+ /* disable alternate function in case it's set */
+ rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
/* set the initial output value */
rb532_set_bit(value, offset, gpch->regbase + GPIOD);
@@ -233,10 +174,11 @@ EXPORT_SYMBOL(rb532_gpio_set_istat);
/*
* Configure GPIO alternate function
*/
-static void rb532_gpio_set_func(int bit, unsigned gpio)
+void rb532_gpio_set_func(unsigned gpio)
{
- rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
+ rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
}
+EXPORT_SYMBOL(rb532_gpio_set_func);
int __init rb532_gpio_init(void)
{
@@ -253,20 +195,6 @@ int __init rb532_gpio_init(void)
/* Register our GPIO chip */
gpiochip_add(&rb532_gpio_chip->chip);
- r = rb532_dev3_ctl_res;
- dev3.base = ioremap_nocache(r->start, r->end - r->start);
-
- if (!dev3.base) {
- printk(KERN_ERR "rb532: cannot remap device controller 3\n");
- return -ENXIO;
- }
-
- /* configure CF_GPIO_NUM as CFRDY IRQ source */
- rb532_gpio_set_func(0, CF_GPIO_NUM);
- rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
- rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
- rb532_gpio_set_istat(0, CF_GPIO_NUM);
-
return 0;
}
arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index 549b46d2fcee3574ac823fd6425ae049c38329bc..53eeb5e7bc5bf4e0b4b3d8efe3f1dbaa1c9e7e9a 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -46,6 +46,7 @@
#include <asm/system.h>
#include <asm/mach-rc32434/irq.h>
+#include <asm/mach-rc32434/gpio.h>
struct intr_group {
u32 mask; /* mask of valid bits in pending/mask registers */
@@ -150,6 +151,9 @@ static void rb532_disable_irq(unsigned int irq_nr)
mask |= intr_bit;
WRITE_MASK(addr, mask);
+ if (group == GPIO_MAPPED_IRQ_GROUP)
+ rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
+
/*
* if there are no more interrupts enabled in this
* group, disable corresponding IP
@@ -165,12 +169,35 @@ static void rb532_mask_and_ack_irq(unsigned int irq_nr)
ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
}
+static int rb532_set_type(unsigned int irq_nr, unsigned type)
+{
+ int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE;
+ int group = irq_to_group(irq_nr);
+
+ if (group != GPIO_MAPPED_IRQ_GROUP)
+ return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
+
+ switch (type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ rb532_gpio_set_ilevel(1, gpio);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ rb532_gpio_set_ilevel(0, gpio);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static struct irq_chip rc32434_irq_type = {
.name = "RB532",
.ack = rb532_disable_irq,
.mask = rb532_disable_irq,
.mask_ack = rb532_mask_and_ack_irq,
.unmask = rb532_enable_irq,
+ .set_type = rb532_set_type,
};
void __init arch_init_irq(void)
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
index 3e0d7ec3a5795315830f8033a542de360fd1f1b5..00ed19f0bdb56e4a9045ba7e2f7388562978d6a4 100644
--- a/arch/mips/rb532/serial.c
+++ b/arch/mips/rb532/serial.c
@@ -36,7 +36,7 @@
extern unsigned int idt_cpu_freq;
static struct uart_port rb532_uart = {
- .type = PORT_16550A,
+ .flags = UPF_BOOT_AUTOCONF,
.line = 0,
.irq = UART0_IRQ,
.iotype = UPIO_MEM,
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 6c0049a5bbc145d644a7cfc1636d8b807c6728d9..55440967b3a88ddaef9d07cef1e79263f5648d7b 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -435,6 +435,28 @@ void __init tx4939_ata_init(void)
platform_device_register(&ata1_dev);
}
+void __init tx4939_rtc_init(void)
+{
+ static struct resource res[] = {
+ {
+ .start = TX4939_RTC_REG & 0xfffffffffULL,
+ .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = TXX9_IRQ_BASE + TX4939_IR_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+ static struct platform_device rtc_dev = {
+ .name = "tx4939rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(res),
+ .resource = res,
+ };
+
+ platform_device_register(&rtc_dev);
+}
+
static void __init tx4939_stop_unused_modules(void)
{
__u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 98fbd9391bf8f7daaba63670970feea77665d30d..656603b85b711964db905fa41bc8b454306a60af 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -336,6 +336,7 @@ static void __init rbtx4939_device_init(void)
rbtx4939_led_setup();
tx4939_wdt_init();
tx4939_ata_init();
+ tx4939_rtc_init();
}
static void __init rbtx4939_setup(void)