diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index c8e554eafce355775c96f96e898ebc7ed168ece7..b5cf6457305a5812bf4a973a03453a6bc53b0527 100644
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned
extern unsigned get_434_reg(unsigned reg_offs);
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
extern unsigned char get_latch_u5(void);
+extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
+extern void rb532_gpio_set_istat(int bit, unsigned gpio);
#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index 79e8ef67d0d397eb38ce223cd27160bec0a8a548..f25a8491670329ec0298e97bb8685bea31a7a02b 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -40,12 +40,14 @@
#define BTCS 0x010040
#define BTCOMPARE 0x010044
#define GPIOBASE 0x050000
-#define GPIOCFG 0x050004
-#define GPIOD 0x050008
-#define GPIOILEVEL 0x05000C
-#define GPIOISTAT 0x050010
-#define GPIONMIEN 0x050014
-#define IMASK6 0x038038
+/* Offsets relative to GPIOBASE */
+#define GPIOFUNC 0x00
+#define GPIOCFG 0x04
+#define GPIOD 0x08
+#define GPIOILEVEL 0x0C
+#define GPIOISTAT 0x10
+#define GPIONMIEN 0x14
+#define IMASK6 0x38
#define LO_WPX (1 << 0)
#define LO_ALE (1 << 1)
#define LO_CLE (1 << 2)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index d3bd5c5aa2ecd0ae1fa34c9083debcac6c4107e0..9601ea95054283dc3d3ed42fb14930da9f426c01 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void)
/*
* Initialize the count register as a clocksource
*/
-#ifdef CONFIG_CEVT_R4K
+#ifdef CONFIG_CSRC_R4K
extern int init_mips_clocksource(void);
#else
static inline int init_mips_clocksource(void)
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 86e026f067bc566c2bbd9620763e2ab6428e836a..74fb74583b4e7e83eec6fdb7d328be7436dd4398 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -27,7 +27,7 @@ int __init init_mips_clocksource(void)
if (!cpu_has_counter || !mips_hpt_frequency)
return -ENXIO;
- /* Calclate a somewhat reasonable rating value */
+ /* Calculate a somewhat reasonable rating value */
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c
index 1f602a110e101e9e54bcd4c1426cec9659eaaa23..13adb578211062d99a30c1733e7fb452d49052b2 100644
--- a/arch/mips/mm/sc-ip22.c
+++ b/arch/mips/mm/sc-ip22.c
@@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void)
/* XXX Check with wje if the Indy caches can differenciate between
writeback + invalidate and just invalidate. */
-struct bcache_ops indy_sc_ops = {
+static struct bcache_ops indy_sc_ops = {
.bc_enable = indy_sc_enable,
.bc_disable = indy_sc_disable,
.bc_wback_inv = indy_sc_wback_invalidate,
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 96236bf33838a20ef8ab147472adba28faf51bb9..df9e526312a24ce4772cb3a332dcab66c3927a50 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -22,9 +22,9 @@
#include <linux/init.h>
#include <linux/smp.h>
-#include <asm-mips/addrspace.h>
-#include <asm-mips/mips-boards/launch.h>
-#include <asm-mips/mipsmtregs.h>
+#include <asm/addrspace.h>
+#include <asm/mips-boards/launch.h>
+#include <asm/mipsmtregs.h>
int amon_cpu_avail(int cpu)
{
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 2f22d714d5b09487c5535f49cce0018dcda4d070..c1c29181bd4641de62977a19107a4d5ad64734c0 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = {
/* Resources and device for NAND */
static int rb532_dev_ready(struct mtd_info *mtd)
{
- return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
+ return gpio_get_value(GPIO_RDY);
}
static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 70c4a6726377ded624a426ca683df1511dd62bc2..0e84c8ab6a3932b39adbfbe2cb8144fae39ba51d 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -39,10 +39,6 @@
struct rb532_gpio_chip {
struct gpio_chip chip;
void __iomem *regbase;
- void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
- int (*get_int_level)(struct gpio_chip *chip, unsigned offset);
- void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
- int (*get_int_status)(struct gpio_chip *chip, unsigned offset);
};
struct mpmc_device dev3;
@@ -111,15 +107,47 @@ unsigned char get_latch_u5(void)
}
EXPORT_SYMBOL(get_latch_u5);
+/* rb532_set_bit - sanely set a bit
+ *
+ * bitval: new value for the bit
+ * offset: bit index in the 4 byte address range
+ * ioaddr: 4 byte aligned address being altered
+ */
+static inline void rb532_set_bit(unsigned bitval,
+ unsigned offset, void __iomem *ioaddr)
+{
+ unsigned long flags;
+ u32 val;
+
+ bitval = !!bitval; /* map parameter to {0,1} */
+
+ local_irq_save(flags);
+
+ val = readl(ioaddr);
+ val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */
+ val |= ( bitval << offset ); /* set bit if bitval == 1 */
+ writel(val, ioaddr);
+
+ local_irq_restore(flags);
+}
+
+/* rb532_get_bit - read a bit
+ *
+ * returns the boolean state of the bit, which may be > 1
+ */
+static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
+{
+ return (readl(ioaddr) & (1 << offset));
+}
+
/*
* Return GPIO level */
static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- u32 mask = 1 << offset;
struct rb532_gpio_chip *gpch;
gpch = container_of(chip, struct rb532_gpio_chip, chip);
- return readl(gpch->regbase + GPIOD) & mask;
+ return rb532_get_bit(offset, gpch->regbase + GPIOD);
}
/*
@@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
static void rb532_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
{
- unsigned long flags;
- u32 mask = 1 << offset;
- u32 tmp;
struct rb532_gpio_chip *gpch;
- void __iomem *gpvr;
gpch = container_of(chip, struct rb532_gpio_chip, chip);
- gpvr = gpch->regbase + GPIOD;
-
- local_irq_save(flags);
- tmp = readl(gpvr);
- if (value)
- tmp |= mask;
- else
- tmp &= ~mask;
- writel(tmp, gpvr);
- local_irq_restore(flags);
+ rb532_set_bit(value, offset, gpch->regbase + GPIOD);
}
/*
@@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip,
*/
static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
- unsigned long flags;
- u32 mask = 1 << offset;
- u32 value;
struct rb532_gpio_chip *gpch;
- void __iomem *gpdr;
gpch = container_of(chip, struct rb532_gpio_chip, chip);
- gpdr = gpch->regbase + GPIOCFG;
- local_irq_save(flags);
- value = readl(gpdr);
- value &= ~mask;
- writel(value, gpdr);
- local_irq_restore(flags);
+ if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
+ return 1; /* alternate function, GPIOCFG is ignored */
+ rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
return 0;
}
@@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
static int rb532_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
- unsigned long flags;
- u32 mask = 1 << offset;
- u32 tmp;
struct rb532_gpio_chip *gpch;
- void __iomem *gpdr;
gpch = container_of(chip, struct rb532_gpio_chip, chip);
- writel(mask, gpch->regbase + GPIOD);
- gpdr = gpch->regbase + GPIOCFG;
- local_irq_save(flags);
- tmp = readl(gpdr);
- tmp |= mask;
- writel(tmp, gpdr);
- local_irq_restore(flags);
+ if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
+ return 1; /* alternate function, GPIOCFG is ignored */
+ /* set the initial output value */
+ rb532_set_bit(value, offset, gpch->regbase + GPIOD);
+
+ rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
return 0;
}
-/*
- * Set the GPIO interrupt level
- */
-static void rb532_gpio_set_int_level(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- unsigned long flags;
- u32 mask = 1 << offset;
- u32 tmp;
- struct rb532_gpio_chip *gpch;
- void __iomem *gpil;
-
- gpch = container_of(chip, struct rb532_gpio_chip, chip);
- gpil = gpch->regbase + GPIOILEVEL;
-
- local_irq_save(flags);
- tmp = readl(gpil);
- if (value)
- tmp |= mask;
- else
- tmp &= ~mask;
- writel(tmp, gpil);
- local_irq_restore(flags);
-}
+static struct rb532_gpio_chip rb532_gpio_chip[] = {
+ [0] = {
+ .chip = {
+ .label = "gpio0",
+ .direction_input = rb532_gpio_direction_input,
+ .direction_output = rb532_gpio_direction_output,
+ .get = rb532_gpio_get,
+ .set = rb532_gpio_set,
+ .base = 0,
+ .ngpio = 32,
+ },
+ },
+};
/*
- * Get the GPIO interrupt level
+ * Set GPIO interrupt level
*/
-static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
+void rb532_gpio_set_ilevel(int bit, unsigned gpio)
{
- u32 mask = 1 << offset;
- struct rb532_gpio_chip *gpch;
-
- gpch = container_of(chip, struct rb532_gpio_chip, chip);
- return readl(gpch->regbase + GPIOILEVEL) & mask;
+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
}
+EXPORT_SYMBOL(rb532_gpio_set_ilevel);
/*
- * Set the GPIO interrupt status
+ * Set GPIO interrupt status
*/
-static void rb532_gpio_set_int_status(struct gpio_chip *chip,
- unsigned offset, int value)
+void rb532_gpio_set_istat(int bit, unsigned gpio)
{
- unsigned long flags;
- u32 mask = 1 << offset;
- u32 tmp;
- struct rb532_gpio_chip *gpch;
- void __iomem *gpis;
-
- gpch = container_of(chip, struct rb532_gpio_chip, chip);
- gpis = gpch->regbase + GPIOISTAT;
-
- local_irq_save(flags);
- tmp = readl(gpis);
- if (value)
- tmp |= mask;
- else
- tmp &= ~mask;
- writel(tmp, gpis);
- local_irq_restore(flags);
+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
}
+EXPORT_SYMBOL(rb532_gpio_set_istat);
/*
- * Get the GPIO interrupt status
+ * Configure GPIO alternate function
*/
-static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
+static void rb532_gpio_set_func(int bit, unsigned gpio)
{
- u32 mask = 1 << offset;
- struct rb532_gpio_chip *gpch;
-
- gpch = container_of(chip, struct rb532_gpio_chip, chip);
- return readl(gpch->regbase + GPIOISTAT) & mask;
+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
}
-static struct rb532_gpio_chip rb532_gpio_chip[] = {
- [0] = {
- .chip = {
- .label = "gpio0",
- .direction_input = rb532_gpio_direction_input,
- .direction_output = rb532_gpio_direction_output,
- .get = rb532_gpio_get,
- .set = rb532_gpio_set,
- .base = 0,
- .ngpio = 32,
- },
- .get_int_level = rb532_gpio_get_int_level,
- .set_int_level = rb532_gpio_set_int_level,
- .get_int_status = rb532_gpio_get_int_status,
- .set_int_status = rb532_gpio_set_int_status,
- },
-};
-
int __init rb532_gpio_init(void)
{
struct resource *r;
@@ -310,9 +261,11 @@ int __init rb532_gpio_init(void)
return -ENXIO;
}
- /* Set the interrupt status and level for the CF pin */
- rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1);
- rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0);
+ /* configure CF_GPIO_NUM as CFRDY IRQ source */
+ rb532_gpio_set_func(0, CF_GPIO_NUM);
+ rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
+ rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
+ rb532_gpio_set_istat(0, CF_GPIO_NUM);
return 0;
}