From fde97822a295da9dffa4af643b49a58ffc4516ad Mon Sep 17 00:00:00 2001 From: Ralf Baechle <ralf@linux-mips.org> Date: Fri, 6 Jul 2007 14:40:05 +0100 Subject: [PATCH] [MIPS] Add macros to encode processor revisions. Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- include/asm-mips/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf845b26..2924069075e0a 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -124,6 +124,17 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +/* + * Older processors used to encode processor version and revision in two + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as + * the patch number. *ARGH* + */ +#define PRID_REV_ENCODE_44(ver, rev) \ + ((ver) << 4 | (rev)) +#define PRID_REV_ENCODE_332(ver, rev, patch) \ + ((ver) << 5 | (rev) << 2 | (patch)) + /* * FPU implementation/revision register (CP1 control register 0). * -- GitLab