Skip to content
Snippets Groups Projects

Draft: WIP Kontron i.MX8MM/MP OSM-S Devicetree Improvements

Closed Draft: WIP Kontron i.MX8MM/MP OSM-S Devicetree Improvements
feature/v6.1-ktn/kontron-mx8m-osm-improvements into v6.1-ktn
Closed Frieder Schrempf requested to merge feature/v6.1-ktn/kontron-mx8m-osm-improvements into v6.1-ktn
Compare
and
Show latest version
2 files
+ 239
− 137
Compare changes
  • Side-by-side
  • Inline
Files
2
arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
+ 4
− 128
@@ -46,9 +46,6 @@ reg_vcc_panel: regulator-vcc-panel {
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
eeram@0 {
@@ -58,9 +55,9 @@ eeram@0 {
};
};
&eqos { /* Second ethernet */
&eqos { /* Second ethernet (OSM-S ETH_B) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-0 = <&pinctrl_eqos_rgmii>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
@@ -82,9 +79,9 @@ ethphy1: ethernet-phy@1 {
};
};
&fec { /* First ethernet */
&fec { /* First ethernet (OSM-S ETH_A) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
pinctrl-0 = <&pinctrl_enet_rgmii>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
@@ -106,8 +103,6 @@ ethphy0: ethernet-phy@1 {
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
@@ -184,11 +179,6 @@ &hdmi_tx_phy {
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
usb-hub@2c {
@@ -201,12 +191,6 @@ usb-hub@2c {
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -291,53 +275,6 @@ &usdhc2 {
};
&iomuxc {
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46
@@ -350,13 +287,6 @@ MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154
MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x46
@@ -370,60 +300,6 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46
>;
};
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x46
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x46
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x46
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x46
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x46
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x46
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x46
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x46
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x46
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x46
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84
>;
};
pinctrl_reg_vcc_panel: regvccpanelgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x19