diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 1e97c697ebd8925d3bbc516e54525ce9b4130857..704f65b09372dfbc87f4c98a5dcd3ba1d4a23d71 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -348,6 +348,7 @@ config ARCH_B4420 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_B4860 bool @@ -370,6 +371,7 @@ config ARCH_B4860 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_BSC9131 bool @@ -727,6 +729,7 @@ config ARCH_P5020 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_P5040 bool @@ -746,6 +749,7 @@ config ARCH_P5040 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_QEMU_E500 bool @@ -833,6 +837,7 @@ config ARCH_T2080 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_T2081 bool @@ -851,6 +856,7 @@ config ARCH_T2081 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_T4160 bool @@ -870,6 +876,7 @@ config ARCH_T4160 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config ARCH_T4240 bool @@ -890,6 +897,7 @@ config ARCH_T4240 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64 config BOOKE bool @@ -1210,6 +1218,9 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +config SYS_PPC64 + bool + config SYS_PPC_E500_USE_DEBUG_TLB bool diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8cde05ce1bb8f2642a6107815206f6fc7e4c3e0e..6fd218a428120817c932c48742bea41dee2e339f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -172,7 +172,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -191,7 +190,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 #elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_PPC64 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_NUM_FMAN 2 @@ -233,7 +231,6 @@ #define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ @@ -277,7 +274,6 @@ #define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ @@ -388,7 +384,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d4a7e4dcb3fc4331be56a1f939fe095836d3cda7..1388684e53197ce983e467e1b06cda498314d3e0 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7132,7 +7132,6 @@ CONFIG_SYS_POST_WATCHDOG CONFIG_SYS_POST_WORD_ADDR CONFIG_SYS_POWER_MANAGER CONFIG_SYS_PPC4XX_USB_ADDR -CONFIG_SYS_PPC64 CONFIG_SYS_PPC_DDR_WIMGE CONFIG_SYS_PQSPAR CONFIG_SYS_PRELIM_OR_AM