Merge git://git.denx.de/u-boot-marvell

arch/arm/Kconfig

@@ -102,6 +102,11 @@ config KIRKWOOD
 	bool "Marvell Kirkwood"
 	select CPU_ARM926EJS
 
+config TARGET_DB_88F6820_GP
+	bool "Support DB-88F6820-GP"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_DB_MV784MP_GP
 	bool "Support db-mv784mp-gp"
 	select CPU_V7
@@ -855,6 +860,7 @@ source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-88f6820-gp/Kconfig"
 source "board/Marvell/db-mv784mp-gp/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/altera/socfpga/Kconfig"

arch/arm/Makefile

@@ -48,6 +48,7 @@ machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)		+= kirkwood
+machine-$(CONFIG_ARMADA_XP)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
@@ -85,8 +86,8 @@ libs-y += arch/arm/imx-common/
 endif
 endif
 
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
-libs-y += arch/arm/mvebu-common/
+ifneq (,$(filter $(SOC), kirkwood))
+libs-y += arch/arm/mach-mvebu/
 endif
 
 # deprecated

arch/arm/cpu/armv7/Makefile

@@ -38,7 +38,6 @@ obj-y += s5p-common/
 endif
 
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
-obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/

arch/arm/cpu/armv7/armada-xp/Makefile → arch/arm/mach-mvebu/Makefile

 #
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifdef CONFIG_KIRKWOOD
+
+obj-y	= dram.o
+obj-y	+= gpio.o
+obj-y	+= timer.o
+
+else
+
 obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= gpio.o
+obj-y	+= mbus.o
+obj-y	+= timer.o
 obj-$(CONFIG_SPL_BUILD) += spl.o
 obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+
+obj-y	+= serdes/
+endif

arch/arm/cpu/armv7/armada-xp/cpu.c → arch/arm/mach-mvebu/cpu.c

 /*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored)
 		;
 }
 
+int mvebu_soc_family(void)
+{
+	u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+
+	if (devid == SOC_MV78460_ID)
+		return MVEBU_SOC_AXP;
+
+	if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
+	    devid == SOC_88F6828_ID)
+		return MVEBU_SOC_A38X;
+
+	return MVEBU_SOC_UNKNOWN;
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
@@ -52,23 +66,48 @@ int print_cpuinfo(void)
 	case SOC_MV78460_ID:
 		puts("MV78460-");
 		break;
-	default:
-		puts("Unknown-");
+	case SOC_88F6810_ID:
+		puts("MV88F6810-");
 		break;
-	}
-
-	switch (revid) {
-	case 1:
-		puts("A0\n");
+	case SOC_88F6820_ID:
+		puts("MV88F6820-");
 		break;
-	case 2:
-		puts("B0\n");
+	case SOC_88F6828_ID:
+		puts("MV88F6828-");
 		break;
 	default:
-		puts("??\n");
+		puts("Unknown-");
 		break;
 	}
 
+	if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+		switch (revid) {
+		case 1:
+			puts("A0\n");
+			break;
+		case 2:
+			puts("B0\n");
+			break;
+		default:
+			printf("?? (%x)\n", revid);
+			break;
+		}
+	}
+
+	if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+		switch (revid) {
+		case MV_88F68XX_Z1_ID:
+			puts("Z1\n");
+			break;
+		case MV_88F68XX_A0_ID:
+			puts("A0\n");
+			break;
+		default:
+			printf("?? (%x)\n", revid);
+			break;
+		}
+	}
+
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -145,11 +184,13 @@ int arch_cpu_init(void)
 	 */
 	mvebu_mbus_probe(NULL, 0);
 
-	/*
-	 * Now the SDRAM access windows can be reconfigured using
-	 * the information in the SDRAM scratch pad registers
-	 */
-	update_sdram_window_sizes();
+	if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+		/*
+		 * Now the SDRAM access windows can be reconfigured using
+		 * the information in the SDRAM scratch pad registers
+		 */
+		update_sdram_window_sizes();
+	}
 
 	/*
 	 * Finally the mbus windows can be configured with the
@@ -175,10 +216,22 @@ int arch_misc_init(void)
 #ifdef CONFIG_MVNETA
 int cpu_eth_init(bd_t *bis)
 {
-	mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
-	mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
-	mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
-	mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
+	u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
+			    MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
+	u8 phy_addr[] = CONFIG_PHY_ADDR;
+	int i;
+
+	/*
+	 * Only Armada XP supports all 4 ethernet interfaces. A38x has
+	 * slightly different base addresses for its 2-3 interfaces.
+	 */
+	if (mvebu_soc_family() != MVEBU_SOC_AXP) {
+		enet_base[1] = MVEBU_EGIGA2_BASE;
+		enet_base[2] = MVEBU_EGIGA3_BASE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
+		mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
 
 	return 0;
 }
@@ -187,6 +240,9 @@ int cpu_eth_init(bd_t *bis)
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+	/* Avoid problem with e.g. neta ethernet driver */
+	invalidate_dcache_all();
+
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 }

arch/arm/include/asm/arch-armada-xp/config.h → arch/arm/mach-mvebu/include/mach/config.h

@@ -9,15 +9,17 @@
 /*
  * This file should be included in board config header file.
  *
- * It supports common definitions for Armada XP platforms
+ * It supports common definitions for MVEBU platforms
  */
 
-#ifndef _ARMADA_XP_CONFIG_H
-#define _ARMADA_XP_CONFIG_H
+#ifndef _MVEBU_CONFIG_H
+#define _MVEBU_CONFIG_H
 
 #include <asm/arch/soc.h>
 
+#if defined(CONFIG_ARMADA_XP)
 #define MV88F78X60 /* for the DDR training bin_hdr code */
+#endif
 
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
@@ -33,8 +35,6 @@
 /* Add target to build it automatically upon "make" */
 #ifdef CONFIG_SPL
 #define CONFIG_BUILD_TARGET	"u-boot-spl.kwb"
-#else
-#define CONFIG_BUILD_TARGET	"u-boot.kwb"
 #endif
 
 /* end of 16M scrubbed by training in bootrom */
@@ -83,4 +83,9 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 #endif
 
-#endif /* _ARMADA_XP_CONFIG_H */
+/* Common SPL configuration */
+#ifndef CONFIG_SPL_LDSCRIPT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-mvebu/u-boot-spl.lds"
+#endif
+
+#endif /* __MVEBU_CONFIG_H */

arch/arm/include/asm/arch-armada-xp/cpu.h → arch/arm/mach-mvebu/include/mach/cpu.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _ARMADA_XP_CPU_H
-#define _ARMADA_XP_CPU_H
+#ifndef _MVEBU_CPU_H
+#define _MVEBU_CPU_H
 
 #include <asm/system.h>
 
@@ -56,6 +56,12 @@ enum cpu_attrib {
 	CPU_ATTR_DEV_CS3 = 0x37,
 };
 
+enum {
+	MVEBU_SOC_AXP,
+	MVEBU_SOC_A38X,
+	MVEBU_SOC_UNKNOWN,
+};
+
 /*
  * Default Device Address MAP BAR values
  */
@@ -106,6 +112,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
 
 /*
  * Highspeed SERDES PHY config init, ported from bin_hdr
@@ -120,4 +127,4 @@ int serdes_phy_config(void);
  */
 int ddr3_init(void);
 #endif /* __ASSEMBLY__ */
-#endif /* _ARMADA_XP_CPU_H */
+#endif /* _MVEBU_CPU_H */

arch/arm/include/asm/arch-armada-xp/soc.h → arch/arm/mach-mvebu/include/mach/soc.h

@@ -8,10 +8,17 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _ASM_ARCH_ARMADA_XP_H
-#define _ASM_ARCH_ARMADA_XP_H
+#ifndef _MVEBU_SOC_H
+#define _MVEBU_SOC_H
 
 #define SOC_MV78460_ID		0x7846
+#define SOC_88F6810_ID		0x6810
+#define SOC_88F6820_ID		0x6820
+#define SOC_88F6828_ID		0x6828
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID	0x0
+#define MV_88F68XX_A0_ID	0x4
 
 /* TCLK Core Clock definition */
 #ifndef CONFIG_SYS_TCLK
@@ -25,6 +32,8 @@
 #define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
 
 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
+#define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
+#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_SPI_BASE		(MVEBU_REGISTER(0x10600))
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
 #define MVEBU_UART0_BASE	(MVEBU_REGISTER(0x12000))
@@ -46,12 +55,9 @@
 #define SDRAM_MAX_CS		4
 #define SDRAM_ADDR_MASK		0xFF000000
 
-/* Armada XP GbE controller has 4 ports */
-#define MAX_MVNETA_DEVS		4
-
-/* Kirkwood CPU memory windows */
+/* MVEBU CPU memory windows */
 #define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
 #define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
 #define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
 
-#endif /* _ASM_ARCH_ARMADA_XP_H */
+#endif /* _MVEBU_SOC_H */

arch/arm/mvebu-common/mbus.c → arch/arm/mach-mvebu/mbus.c

@@ -341,9 +341,6 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
 			w = &mbus_dram_info.cs[cs++];
 			w->cs_index = i;
 			w->mbus_attr = 0xf & ~(1 << i);
-#if defined(CONFIG_ARMADA_XP)
-			w->mbus_attr |= ATTR_HW_COHERENCY;
-#endif
 			w->base = base & DDR_BASE_CS_LOW_MASK;
 			w->size = (size | ~DDR_SIZE_MASK) + 1;
 		}