SPL: ARM: spear: Add SPL support for SPEAr600 platform

This patch adds SPL support for SPEAr600. Currently only SNOR
(Serial NOR) flash support is included. Other boot devices
(NAND, MMC, USB ...) may be added with later patches.

Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>

arch/arm/cpu/arm926ejs/spear/Makefile

@@ -25,17 +25,27 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	:= cpu.o \
+COBJS-y	:= cpu.o \
 	   reset.o \
 	   timer.o
-SOBJS	:=
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= spl.o spl_boot.o
+COBJS-$(CONFIG_SPEAR600) += spear600.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+endif
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
 

arch/arm/cpu/arm926ejs/spear/spear600.c

+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_defs.h>
+
+#define FALSE				0
+#define TRUE				(!FALSE)
+
+static void sel_1v8(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000003;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000010;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+static void sel_2v5(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000003;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000010;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+/*
+ * plat_ddr_init:
+ */
+void plat_ddr_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddrpad;
+	u32 core3v3, ddr1v8, ddr2v5;
+
+	/* DDR pad register configurations */
+	ddrpad = readl(&misc_p->ddr_pad);
+	ddrpad &= ~DDR_PAD_CNF_MSK;
+
+#if (CONFIG_DDR_HCLK)
+	ddrpad |= 0xEAAB;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpad |= 0xEAAD;
+#elif (CONFIG_DDR_PLL2)
+	ddrpad |= 0xEAAD;
+#endif
+	writel(ddrpad, &misc_p->ddr_pad);
+
+	/* Compensation register configurations */
+	core3v3 = readl(&misc_p->core_3v3_compensation);
+	core3v3 &= 0x8080ffe0;
+	core3v3 |= 0x78000002;
+	writel(core3v3, &misc_p->core_3v3_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000004;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000004;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
+		/* Software memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
+			sel_1v8();
+		else
+			sel_2v5();
+	} else {
+		/* Hardware memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
+			sel_1v8();
+		else
+			sel_2v5();
+	}
+}
+
+/*
+ * soc_init:
+ */
+void soc_init(void)
+{
+	/* Nothing to be done for SPEAr600 */
+}
+
+/*
+ * xxx_boot_selected:
+ *
+ * return TRUE if the particular booting option is selected
+ * return FALSE otherwise
+ */
+static u32 read_bootstrap(void)
+{
+	return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
+		& CONFIG_SPEAR_BOOTSTRAPMASK;
+}
+
+int snor_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (SNOR_BOOT_SUPPORTED) {
+		/* Check whether SNOR boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
+			CONFIG_SPEAR_ONLYSNORBOOT)
+			return TRUE;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return TRUE;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return TRUE;
+	}
+
+	return FALSE;
+}
+
+int nand_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (NAND_BOOT_SUPPORTED) {
+		/* Check whether NAND boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return TRUE;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return TRUE;
+	}
+
+	return FALSE;
+}
+
+int pnor_boot_selected(void)
+{
+	/* Parallel NOR boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int usb_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (USB_BOOT_SUPPORTED) {
+		/* Check whether USB boot is selected */
+		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+			return TRUE;
+	}
+
+	return FALSE;
+}
+
+int tftp_boot_selected(void)
+{
+	/* TFTP boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int uart_boot_selected(void)
+{
+	/* UART boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int spi_boot_selected(void)
+{
+	/* SPI boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int i2c_boot_selected(void)
+{
+	/* I2C boot is not selected in any SPEAr600 revision */
+	return FALSE;
+}
+
+int mmc_boot_selected(void)
+{
+	return FALSE;
+}
+
+void plat_late_init(void)
+{
+	spear_late_init();
+}

arch/arm/cpu/arm926ejs/spear/spl.c

+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_syscntl.h>
+
+inline void hang(void)
+{
+	serial_puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+static void ddr_clock_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 clkenb, ddrpll;
+
+	clkenb = readl(&misc_p->periph1_clken);
+	clkenb &= ~PERIPH_MPMCMSK;
+	clkenb |= PERIPH_MPMC_WE;
+
+	/* Intentionally done twice */
+	writel(clkenb, &misc_p->periph1_clken);
+	writel(clkenb, &misc_p->periph1_clken);
+
+	ddrpll = readl(&misc_p->pll_ctr_reg);
+	ddrpll &= ~MEM_CLK_SEL_MSK;
+#if (CONFIG_DDR_HCLK)
+	ddrpll |= MEM_CLK_HCLK;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpll |= MEM_CLK_2HCLK;
+#elif (CONFIG_DDR_PLL2)
+	ddrpll |= MEM_CLK_PLL2;
+#else
+#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#endif
+	writel(ddrpll, &misc_p->pll_ctr_reg);
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+			&misc_p->periph1_clken);
+}
+
+static void mpmc_init_values(void)
+{
+	u32 i;
+	u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+	u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+	for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
+		writel(*mpmc_val_p, mpmc_reg_p);
+
+	mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+
+	/*
+	 * MPMC controller start
+	 * MPMC waiting for DLLLOCKREG high
+	 */
+	writel(0x01000100, &mpmc_reg_p[7]);
+
+	while (!(readl(&mpmc_reg_p[3]) & 0x10000))
+		;
+}
+
+static void mpmc_init(void)
+{
+	/* Clock related settings for DDR */
+	ddr_clock_init();
+
+	/*
+	 * DDR pad register bits are different for different SoCs
+	 * Compensation values are also handled separately
+	 */
+	plat_ddr_init();
+
+	/* Initialize mpmc register values */
+	mpmc_init_values();
+}
+
+static void pll_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Initialize PLLs */
+	writel(FREQ_332, &misc_p->pll1_frq);
+	writel(0x1C0A, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+	writel(0x1C06, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+
+	writel(FREQ_332, &misc_p->pll2_frq);
+	writel(0x1C0A, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+	writel(0x1C06, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+
+	/* wait for pll locks */
+	while (!(readl(&misc_p->pll1_cntl) & 0x1))
+		;
+	while (!(readl(&misc_p->pll2_cntl) & 0x1))
+		;
+}
+
+static void mac_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
+			&misc_p->periph1_clken);
+
+	writel(SYNTH23, &misc_p->gmac_synth_clk);
+
+	switch (get_socrev()) {
+	case SOC_SPEAR600_AA:
+	case SOC_SPEAR600_AB:
+	case SOC_SPEAR600_BA:
+	case SOC_SPEAR600_BB:
+	case SOC_SPEAR600_BC:
+	case SOC_SPEAR600_BD:
+		writel(0x0, &misc_p->gmac_ctr_reg);
+		break;
+
+	case SOC_SPEAR300:
+	case SOC_SPEAR310:
+	case SOC_SPEAR320:
+		writel(0x4, &misc_p->gmac_ctr_reg);
+		break;
+	}
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
+			&misc_p->periph1_clken);
+
+	writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
+			&misc_p->periph1_rst);
+	writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
+			&misc_p->periph1_rst);
+}
+
+static void sys_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct syscntl_regs *syscntl_p =
+		(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	/* Set system state to SLOW */
+	writel(SLOW, &syscntl_p->scctrl);
+	writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+
+	/* Initialize PLLs */
+	pll_init();
+
+	/*
+	 * Ethernet configuration
+	 * To be done only if the tftp boot is not selected already
+	 * Boot code ensures the correct configuration in tftp booting
+	 */
+	if (!tftp_boot_selected())
+		mac_init();
+
+	writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+	writel(0x555, &misc_p->amba_clk_cfg);
+
+	writel(NORMAL, &syscntl_p->scctrl);
+
+	/* Wait for system to switch to normal mode */
+	while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
+		!= NORMAL)
+		;
+}
+
+/*
+ * get_socrev
+ *
+ * Get SoC Revision.
+ * @return SOC_SPEARXXX
+ */
+int get_socrev(void)
+{
+#if defined(CONFIG_SPEAR600)
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 soc_id = readl(&misc_p->soc_core_id);
+	u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
+	u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
+
+	if ((pri_socid == 'B') && (sec_socid == 'B'))
+		return SOC_SPEAR600_BB;
+	else if ((pri_socid == 'B') && (sec_socid == 'C'))
+		return SOC_SPEAR600_BC;
+	else if ((pri_socid == 'B') && (sec_socid == 'D'))
+		return SOC_SPEAR600_BD;
+	else if (soc_id == 0)
+		return SOC_SPEAR600_BA;
+	else
+		return SOC_SPEAR_NA;
+#elif defined(CONFIG_SPEAR300)
+	return SOC_SPEAR300;
+#elif defined(CONFIG_SPEAR310)
+	return SOC_SPEAR310;
+#elif defined(CONFIG_SPEAR320)
+	return SOC_SPEAR320;
+#endif
+}
+
+void lowlevel_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	const char *u_boot_rev = U_BOOT_VERSION;
+
+	/* Initialize PLLs */
+	sys_init();
+
+	/* Initialize UART */
+	serial_init();
+
+	/* Print U-Boot SPL version string */
+	serial_puts("\nU-Boot SPL ");
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+	serial_puts(u_boot_rev);
+	serial_puts(" (");
+	serial_puts(U_BOOT_DATE);
+	serial_puts(" - ");
+	serial_puts(U_BOOT_TIME);
+	serial_puts(")\n");
+
+#if defined(CONFIG_OS_BOOT)
+	writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
+			&misc_p->periph1_clken);
+#endif
+
+	/* Enable IPs (release reset) */
+	writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+
+	/* Initialize MPMC */
+	serial_puts("Configure DDR\n");
+	mpmc_init();
+
+	/* SoC specific initialization */
+	soc_init();
+}
+
+void spear_late_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(0x80000007, &misc_p->arb_icm_ml1);
+	writel(0x80000007, &misc_p->arb_icm_ml2);
+	writel(0x80000007, &misc_p->arb_icm_ml3);
+	writel(0x80000007, &misc_p->arb_icm_ml4);
+	writel(0x80000007, &misc_p->arb_icm_ml5);
+	writel(0x80000007, &misc_p->arb_icm_ml6);
+	writel(0x80000007, &misc_p->arb_icm_ml7);
+	writel(0x80000007, &misc_p->arb_icm_ml8);
+	writel(0x80000007, &misc_p->arb_icm_ml9);
+}

arch/arm/cpu/arm926ejs/spear/spl_boot.c

+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/spr_defs.h>
+#include <linux/mtd/st_smi.h>
+
+static const char kernel_name[] = "Linux";
+static const char loader_name[] = "U-Boot";
+
+int image_check_header(image_header_t *hdr, const char *name)
+{
+	if (image_check_magic(hdr) &&
+	    (!strncmp(image_get_name(hdr), name, strlen(name))) &&
+	    image_check_hcrc(hdr)) {
+		return 1;
+	}
+	return 0;
+}
+
+int image_check_data(image_header_t *hdr)
+{
+	if (image_check_dcrc(hdr))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+void snor_init(void)
+{
+	struct smi_regs *const smicntl =
+		(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+	       &smicntl->smi_cr1);
+}
+
+static int snor_image_load(u8 *load_addr, void (**image_p)(void),
+			   const char *image_name)
+{
+	image_header_t *header;
+
+	/*
+	 * Since calculating the crc in the SNOR flash does not
+	 * work, we copy the image to the destination address
+	 * minus the header size. And point the header to this
+	 * new destination. This will not work for address 0
+	 * of course.
+	 */
+	header = (image_header_t *)load_addr;
+	memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
+	       (const ulong *)load_addr,
+	       image_get_data_size(header) + sizeof(image_header_t));
+	header = (image_header_t *)(image_get_load(header) -
+				    sizeof(image_header_t));
+
+	if (image_check_header(header, image_name)) {
+		if (image_check_data(header)) {
+			/* Jump to boot image */
+			*image_p = (void *)image_get_load(header);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static void boot_image(void (*image)(void))
+{
+	void (*funcp)(void) __noreturn = (void *)image;
+
+	(*funcp)();
+}
+
+/*
+ * spl_boot:
+ *
+ * All supported booting types of all supported SoCs are listed here.
+ * Generic readback APIs are provided for each supported booting type
+ * eg. nand_read_skip_bad
+ */
+u32 spl_boot(void)
+{
+	void (*image)(void);
+
+#ifdef CONFIG_SPEAR_USBTTY
+	plat_late_init();
+	return 1;
+#endif
+
+	/*
+	 * All the supported booting devices are listed here. Each of
+	 * the booting type supported by the platform would define the
+	 * macro xxx_BOOT_SUPPORTED to TRUE.
+	 */
+
+	if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
+		/* SNOR-SMI initialization */
+		snor_init();
+
+		serial_puts("Booting via SNOR\n");
+		/* Serial NOR booting */
+		if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
+					    &image, loader_name)) {
+			/* Platform related late initialasations */
+			plat_late_init();
+
+			/* Jump to boot image */
+			serial_puts("Jumping to U-Boot\n");
+			boot_image(image);
+			return 1;
+		}
+	}
+
+	if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
+		/* NAND booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
+		/* PNOR booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
+		/* MMC booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
+		/* SPI booting */
+		/* Not supported for any platform as of now */
+		return 0;
+	}
+
+	if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
+		/* I2C booting */
+		/* Not supported for any platform as of now */
+		return 0;
+	}
+
+	/*
+	 * All booting types without memory are listed as below
+	 * Control has to be returned to BootROM in case of all
+	 * the following booting scenarios
+	 */
+
+	if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	/* Ideally, the control should not reach here. */
+	hang();
+}

arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c

+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000001,
+	0x00000000,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02030202,
+	0x03000204,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00040800,
+	0x00000000,
+	0x00000f02,
+	0x00001b1b,
+	0x7f000000,
+	0x005f0000,
+	0x1c040b6a,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x000007ff,
+	0x00000000,
+	0x47ec00c8,
+	0x00c8001f,
+	0x00000000,
+	0x0000cd98,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00270000,
+	0x00250027,
+	0x00300000,
+	0x008900b7,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif

arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c

+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+	0x72000000,
+	0x00550000,
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif

arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c

+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x03030301,
+	0x03030303,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02020202,
+	0x03000203,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00030600,
+	0x00000000,
+	0x00000a02,
+	0x00001c1c,
+	0x7f000000,
+	0x005f0000,
+	0x12030743,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x0000050e,
+	0x00000000,
+	0x2d8900c8,
+	0x00c80014,
+	0x00000000,
+	0x00008236,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00400000,
+	0x003a0040,
+	0x00680000,
+	0x00d80120,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif

arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c

+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+#ifdef CONFIG_X600
+	0x02030206,
+#else
+	0x02010106,
+#endif
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+#ifdef CONFIG_X600
+	0x7f000000,
+	0x005c0000,
+#else
+	0x72000000,
+	0x00550000,
+#endif
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif

arch/arm/cpu/arm926ejs/spear/start.S

+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+
+.globl _start
+_start:
+	b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+_software_interrupt:
+_prefetch_abort:
+_data_abort:
+_not_used:
+_irq:
+_fiq:
+	.word infinite_loop
+
+infinite_loop:
+	b	infinite_loop
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * Below are the critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+	stmdb	sp!, {r0-r12,r14}
+	bl	cpu_init_crit
+/*
+ * Clearing bss area is not done in Xloader.
+ * BSS area lies in the DDR location which is not yet initialized
+ * bss is assumed to be uninitialized.
+ */
+	bl	spl_boot
+	ldmia	sp!, {r0-r12,pc}
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * enable instruction cache
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	stmdb	sp!, {lr}
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	ldmia	sp!, {pc}

arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds

+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/arm926ejs/spear/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	_end = .;
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynsym*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.hash*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}

arch/arm/include/asm/arch-spear/hardware.h

@@ -24,37 +24,54 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
-#define CONFIG_SYS_USBD_BASE			(0xE1100000)
-#define CONFIG_SYS_PLUG_BASE			(0xE1200000)
-#define CONFIG_SYS_FIFO_BASE			(0xE1000800)
-#define CONFIG_SYS_SMI_BASE			(0xFC000000)
-#define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
-#define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
-#define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
+#define CONFIG_SYS_USBD_BASE			0xE1100000
+#define CONFIG_SYS_PLUG_BASE			0xE1200000
+#define CONFIG_SYS_FIFO_BASE			0xE1000800
+#define CONFIG_SYS_SMI_BASE			0xFC000000
+#define CONFIG_SPEAR_SYSCNTLBASE		0xFCA00000
+#define CONFIG_SPEAR_TIMERBASE			0xFC800000
+#define CONFIG_SPEAR_MISCBASE			0xFCA80000
 #define CONFIG_SPEAR_ETHBASE			0xE0800000
+#define CONFIG_SPEAR_MPMCBASE			0xFC600000
+#define CONFIG_SSP1_BASE			0xD0100000
+#define CONFIG_SSP2_BASE			0xD0180000
+#define CONFIG_SSP3_BASE			0xD8180000
+#define CONFIG_GPIO_BASE			0xD8100000
 
 #define CONFIG_SYS_NAND_CLE			(1 << 16)
 #define CONFIG_SYS_NAND_ALE			(1 << 17)
 
 #if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE			(0xD0200000)
-#define CONFIG_SYS_FSMC_BASE			(0xD1800000)
+#define CONFIG_SYS_I2C_BASE			0xD0200000
+#define CONFIG_SYS_FSMC_BASE			0xD1800000
+#define CONFIG_FSMC_NAND_BASE			0xD2000000
+
+#define CONFIG_SPEAR_BOOTSTRAPCFG		0xFCA80000
+#define CONFIG_SPEAR_BOOTSTRAPSHFT		16
+#define CONFIG_SPEAR_BOOTSTRAPMASK		0xB
+#define CONFIG_SPEAR_ONLYSNORBOOT		0xA
+#define CONFIG_SPEAR_NORNANDBOOT		0xB
+#define CONFIG_SPEAR_NORNAND8BOOT		0x8
+#define CONFIG_SPEAR_NORNAND16BOOT		0x9
+#define CONFIG_SPEAR_USBBOOT			0x8
+
+#define CONFIG_SPEAR_MPMCREGS			100
 
 #elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SYS_FSMC_BASE			(0x94000000)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#define CONFIG_SYS_FSMC_BASE			0x94000000
 
 #elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SYS_FSMC_BASE			(0x44000000)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#define CONFIG_SYS_FSMC_BASE			0x44000000
 
 #undef CONFIG_SYS_NAND_CLE
 #undef CONFIG_SYS_NAND_ALE
 #define CONFIG_SYS_NAND_CLE			(1 << 17)
 #define CONFIG_SYS_NAND_ALE			(1 << 16)
 
-#define CONFIG_SPEAR_EMIBASE			(0x4F000000)
-#define CONFIG_SPEAR_RASBASE			(0xB4000000)
+#define CONFIG_SPEAR_EMIBASE			0x4F000000
+#define CONFIG_SPEAR_RASBASE			0xB4000000
 
 #define CONFIG_SYS_MACB0_BASE			0xB0000000
 #define CONFIG_SYS_MACB1_BASE			0xB0800000
@@ -62,11 +79,11 @@
 #define CONFIG_SYS_MACB3_BASE			0xB1800000
 
 #elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SYS_FSMC_BASE			(0x4C000000)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#define CONFIG_SYS_FSMC_BASE			0x4C000000
 
-#define CONFIG_SPEAR_EMIBASE			(0x40000000)
-#define CONFIG_SPEAR_RASBASE			(0xB3000000)
+#define CONFIG_SPEAR_EMIBASE			0x40000000
+#define CONFIG_SPEAR_RASBASE			0xB3000000
 
 #define CONFIG_SYS_MACB0_BASE			0xAA000000
 

arch/arm/include/asm/arch-spear/spr_defs.h

@@ -28,6 +28,30 @@ extern int spear_board_init(ulong);
 extern void setfreq(unsigned int, unsigned int);
 extern unsigned int setfreq_sz;
 
+void plat_ddr_init(void);
+void soc_init(void);
+void spear_late_init(void);
+void plat_late_init(void);
+
+int snor_boot_selected(void);
+int nand_boot_selected(void);
+int pnor_boot_selected(void);
+int usb_boot_selected(void);
+int uart_boot_selected(void);
+int tftp_boot_selected(void);
+int i2c_boot_selected(void);
+int spi_boot_selected(void);
+int mmc_boot_selected(void);
+
+extern u32 mpmc_conf_vals[];
+
+struct chip_data {
+	int cpufreq;
+	int dramfreq;
+	int dramtype;
+	uchar version[32];
+};
+
 /* HW mac id in i2c memory definitions */
 #define MAGIC_OFF	0x0
 #define MAGIC_LEN	0x2
@@ -36,4 +60,10 @@ extern unsigned int setfreq_sz;
 #define MAC_OFF		0x2
 #define MAC_LEN		0x6
 
+#define PNOR_WIDTH_8			0
+#define	PNOR_WIDTH_16			1
+#define	PNOR_WIDTH_32			2
+#define PNOR_WIDTH_NUM			3
+#define PNOR_WIDTH_SEARCH		0xff
+
 #endif

arch/arm/include/asm/arch-spear/spr_misc.h

@@ -46,7 +46,7 @@ struct misc_regs {
 	u32 prsc2_clk_cfg;	/* 0x48 */
 	u32 prsc3_clk_cfg;	/* 0x4C */
 	u32 amem_cfg_ctrl;	/* 0x50 */
-	u32 port_cfg_ctrl;	/* 0x54 */
+	u32 expi_clk_cfg;	/* 0x54 */
 	u32 reserved_1;		/* 0x58 */
 	u32 clcd_synth_clk;	/* 0x5C */
 	u32 irda_synth_clk;	/* 0x60 */
@@ -101,6 +101,37 @@ struct misc_regs {
 	u32 ras_gpp2_out;	/* 0x800C */
 };
 
+/* SYNTH_CLK value*/
+#define SYNTH23			0x00020003
+
+/* PLLx_FRQ value */
+#if defined(CONFIG_SPEAR3XX)
+#define FREQ_332		0xA600010C
+#define FREQ_266		0x8500010C
+#elif defined(CONFIG_SPEAR600)
+#define FREQ_332		0xA600010F
+#define FREQ_266		0x8500010F
+#endif
+
+/* PLL_CTR_REG   */
+#define MEM_CLK_SEL_MSK		0x70000000
+#define MEM_CLK_HCLK		0x00000000
+#define MEM_CLK_2HCLK		0x10000000
+#define MEM_CLK_PLL2		0x30000000
+
+#define EXPI_CLK_CFG_LOW_COMPR	0x2000
+#define EXPI_CLK_CFG_CLK_EN	0x0400
+#define EXPI_CLK_CFG_RST	0x0200
+#define EXPI_CLK_SYNT_EN	0x0010
+#define EXPI_CLK_CFG_SEL_PLL2	0x0004
+#define EXPI_CLK_CFG_INT_CLK_EN	0x0001
+
+#define PLL2_CNTL_6UA		0x1c00
+#define PLL2_CNTL_SAMPLE	0x0008
+#define PLL2_CNTL_ENABLE	0x0004
+#define PLL2_CNTL_RESETN	0x0002
+#define PLL2_CNTL_LOCK		0x0001
+
 /* AUTO_CFG_REG value */
 #define MISC_SOCCFGMSK                  0x0000003F
 #define MISC_SOCCFG30                   0x0000000C
@@ -131,9 +162,112 @@ struct misc_regs {
 #define MISC_ETHENB			0x00800000
 #define MISC_SMIENB			0x00200000
 #define MISC_GPT3ENB			0x00010000
+#define MISC_GPIO4ENB			0x00002000
 #define MISC_GPT2ENB			0x00000800
 #define MISC_FSMCENB			0x00000200
 #define MISC_I2CENB			0x00000080
+#define MISC_SSP2ENB			0x00000070
 #define MISC_UART0ENB			0x00000008
 
+/*   PERIPH_CLK_CFG   */
+#define  XTALTIMEEN		0x00000001
+#define  PLLTIMEEN		0x00000002
+#define  CLCDCLK_SYNTH		0x00000000
+#define  CLCDCLK_48MHZ		0x00000004
+#define  CLCDCLK_EXT		0x00000008
+#define  UARTCLK_MASK		(0x1 << 4)
+#define  UARTCLK_48MHZ		0x00000000
+#define  UARTCLK_SYNTH		0x00000010
+#define  IRDACLK_48MHZ		0x00000000
+#define  IRDACLK_SYNTH		0x00000020
+#define  IRDACLK_EXT		0x00000040
+#define  RTC_DISABLE		0x00000080
+#define  GPT1CLK_48MHZ		0x00000000
+#define  GPT1CLK_SYNTH		0x00000100
+#define  GPT2CLK_48MHZ		0x00000000
+#define  GPT2CLK_SYNTH		0x00000200
+#define  GPT3CLK_48MHZ		0x00000000
+#define  GPT3CLK_SYNTH		0x00000400
+#define  GPT4CLK_48MHZ		0x00000000
+#define  GPT4CLK_SYNTH		0x00000800
+#define  GPT5CLK_48MHZ		0x00000000
+#define  GPT5CLK_SYNTH		0x00001000
+#define  GPT1_FREEZE		0x00002000
+#define  GPT2_FREEZE		0x00004000
+#define  GPT3_FREEZE		0x00008000
+#define  GPT4_FREEZE		0x00010000
+#define  GPT5_FREEZE		0x00020000
+
+/*  PERIPH1_CLKEN bits  */
+#define PERIPH_ARM1_WE		0x00000001
+#define PERIPH_ARM1		0x00000002
+#define PERIPH_ARM2		0x00000004
+#define PERIPH_UART1		0x00000008
+#define PERIPH_UART2		0x00000010
+#define PERIPH_SSP1		0x00000020
+#define PERIPH_SSP2		0x00000040
+#define PERIPH_I2C		0x00000080
+#define PERIPH_JPEG		0x00000100
+#define PERIPH_FSMC		0x00000200
+#define PERIPH_FIRDA		0x00000400
+#define PERIPH_GPT4		0x00000800
+#define PERIPH_GPT5		0x00001000
+#define PERIPH_GPIO4		0x00002000
+#define PERIPH_SSP3		0x00004000
+#define PERIPH_ADC		0x00008000
+#define PERIPH_GPT3		0x00010000
+#define PERIPH_RTC		0x00020000
+#define PERIPH_GPIO3		0x00040000
+#define PERIPH_DMA		0x00080000
+#define PERIPH_ROM		0x00100000
+#define PERIPH_SMI		0x00200000
+#define PERIPH_CLCD		0x00400000
+#define PERIPH_GMAC		0x00800000
+#define PERIPH_USBD		0x01000000
+#define PERIPH_USBH1		0x02000000
+#define PERIPH_USBH2		0x04000000
+#define PERIPH_MPMC		0x08000000
+#define PERIPH_RAMW		0x10000000
+#define PERIPH_MPMC_EN		0x20000000
+#define PERIPH_MPMC_WE		0x40000000
+#define PERIPH_MPMCMSK		0x60000000
+
+#define PERIPH_CLK_ALL		0x0FFFFFF8
+#define PERIPH_RST_ALL		0x00000004
+
+/* DDR_PAD values */
+#define DDR_PAD_CNF_MSK		0x0000ffff
+#define DDR_PAD_SW_CONF		0x00060000
+#define DDR_PAD_SSTL_SEL	0x00000001
+#define DDR_PAD_DRAM_TYPE	0x00008000
+
+/* DDR_COMP values */
+#define DDR_COMP_ACCURATE	0x00000010
+
+/* SoC revision stuff */
+#define SOC_PRI_SHFT		16
+#define SOC_SEC_SHFT		8
+
+/* Revision definitions */
+#define SOC_SPEAR_NA		0
+
+/*
+ * The definitons have started from
+ * 101 for SPEAr6xx
+ * 201 for SPEAr3xx
+ * 301 for SPEAr13xx
+ */
+#define SOC_SPEAR600_AA		101
+#define SOC_SPEAR600_AB		102
+#define SOC_SPEAR600_BA		103
+#define SOC_SPEAR600_BB		104
+#define SOC_SPEAR600_BC		105
+#define SOC_SPEAR600_BD		106
+
+#define SOC_SPEAR300		201
+#define SOC_SPEAR310		202
+#define SOC_SPEAR320		203
+
+extern int get_socrev(void);
+
 #endif

arch/arm/include/asm/arch-spear/spr_ssp.h

+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_SSP_H
+#define _SPR_SSP_H
+
+struct ssp_regs {
+	u32 sspcr0;
+	u32 sspcr1;
+	u32 sspdr;
+	u32 sspsr;
+	u32 sspcpsr;
+	u32 sspimsc;
+	u32 sspicr;
+	u32 sspdmacr;
+};
+
+#define SSPCR0_FRF_MOT_SPI	0x0000
+#define SSPCR0_DSS_16BITS	0x000f
+
+#define SSPCR1_SSE		0x0002
+
+#define SSPSR_TNF		0x2
+#define SSPSR_TFE		0x1
+
+#endif

arch/arm/include/asm/arch-spear/spr_syscntl.h

@@ -21,6 +21,9 @@
  * MA 02111-1307 USA
  */
 
+#ifndef __SYSCTRL_H
+#define __SYSCTRL_H
+
 struct syscntl_regs {
 	u32 scctrl;
 	u32 scsysstat;
@@ -36,3 +39,14 @@ struct syscntl_regs {
 	const u32 scperclken;
 	const u32 scperstat;
 };
+
+#define MODE_SHIFT          0x00000003
+
+#define NORMAL              0x00000004
+#define SLOW                0x00000002
+#define DOZE                0x00000001
+#define SLEEP               0x00000000
+
+#define PLL_TIM             0x01FFFFFF
+
+#endif