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Commit 56612bf6 authored by Peng Fan's avatar Peng Fan Committed by Stefano Babic
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imx: mx6sll: update register address


Update register address for i.MX6 SLL

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
parent 36e40142
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...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000 #define M4_BOOTROM_BASE_ADDR 0x007F8000
#else #elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF #define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
...@@ -46,13 +46,9 @@ ...@@ -46,13 +46,9 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */ /* GPV - PL301 configuration ports */
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
#define GPV2_BASE_ADDR 0x00D00000 #define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV3_BASE_ADDR 0x00E00000 #define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000 #define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000 #define GPV5_BASE_ADDR 0x01000000
...@@ -61,6 +57,7 @@ ...@@ -61,6 +57,7 @@
#define PCIE_ARB_END_ADDR 0x08FFFFFF #define PCIE_ARB_END_ADDR 0x08FFFFFF
#else #else
#define GPV2_BASE_ADDR 0x00200000
#define GPV3_BASE_ADDR 0x00300000 #define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000 #define GPV4_BASE_ADDR 0x00800000
#define PCIE_ARB_BASE_ADDR 0x01000000 #define PCIE_ARB_BASE_ADDR 0x01000000
...@@ -96,7 +93,7 @@ ...@@ -96,7 +93,7 @@
#define WEIM_ARB_END_ADDR 0x57FFFFFF #define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000 #define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF #define QSPI0_AMBA_END 0x6FFFFFFF
#else #elif !defined(CONFIG_MX6SLL)
#define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF #define SATA_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_BASE_ADDR 0x02204000
...@@ -111,7 +108,8 @@ ...@@ -111,7 +108,8 @@
#define WEIM_ARB_END_ADDR 0x0FFFFFFF #define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif #endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000 #define MMDC1_ARB_BASE_ADDR 0xC0000000
...@@ -141,19 +139,21 @@ ...@@ -141,19 +139,21 @@
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
#ifdef CONFIG_MX6SL
#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) #define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) #define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) #define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) #define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) #define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#else #define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
#ifndef CONFIG_MX6SX #ifndef CONFIG_MX6SX
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#endif #endif
#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
...@@ -161,7 +161,6 @@ ...@@ -161,7 +161,6 @@
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#endif
#ifndef CONFIG_MX6SX #ifndef CONFIG_MX6SX
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
...@@ -176,6 +175,8 @@ ...@@ -176,6 +175,8 @@
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
/* QOSC on i.MX6SLL */
#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
...@@ -198,11 +199,18 @@ ...@@ -198,11 +199,18 @@
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
#ifdef CONFIG_MX6SL #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#ifdef CONFIG_MX6SLL
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
#elif defined(CONFIG_MX6SL)
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#elif CONFIG_MX6SX #elif defined(CONFIG_MX6SX)
#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
...@@ -215,6 +223,9 @@ ...@@ -215,6 +223,9 @@
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#endif #endif
#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
...@@ -249,7 +260,7 @@ ...@@ -249,7 +260,7 @@
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
/* i.MX6SL */ /* i.MX6SL/SLL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#ifdef CONFIG_MX6UL #ifdef CONFIG_MX6UL
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
...@@ -263,6 +274,10 @@ ...@@ -263,6 +274,10 @@
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#ifdef CONFIG_MX6SLL
#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#endif
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
...@@ -296,6 +311,8 @@ ...@@ -296,6 +311,8 @@
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
/* i.MX6SLL */
#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX #ifdef CONFIG_MX6SX
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
...@@ -334,7 +351,8 @@ ...@@ -334,7 +351,8 @@
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
#define IRAM_SIZE 0x00040000 #define IRAM_SIZE 0x00040000
#else #else
#define IRAM_SIZE 0x00020000 #define IRAM_SIZE 0x00020000
...@@ -348,10 +366,14 @@ ...@@ -348,10 +366,14 @@
/* only for i.MX6SX/UL */ /* only for i.MX6SX/UL */
#define WDOG3_BASE_ADDR ((is_mx6ul() ? \ #define WDOG3_BASE_ADDR ((is_mx6ul() ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
#define LCDIF1_BASE_ADDR ((is_mx6ul()) ? \ #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
MX6SLL_LCDIF_BASE_ADDR : \
(is_cpu_type(MXC_CPU_MX6SL)) ? \
MX6SL_LCDIF_BASE_ADDR : \
((is_cpu_type(MXC_CPU_MX6UL)) ? \
MX6UL_LCDIF1_BASE_ADDR : \ MX6UL_LCDIF1_BASE_ADDR : \
((is_mx6ull()) ? \ ((is_mx6ull()) ? \
MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)) MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
...@@ -672,7 +694,8 @@ struct cspi_regs { ...@@ -672,7 +694,8 @@ struct cspi_regs {
#define MXC_CSPICON_POL 4 /* SCLK polarity */ #define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \ #define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \ ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \ ECSPI2_BASE_ADDR, \
......
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