board: ti: am57xx: Update SR1.1 RGMII0 iodelay timings for x15/GPEVM

Update the timing for RGMII0 interface based on
PCT_DRA75x_DRA74x_SR1.1_v1.3.10 version (Jan 2016). This update
is for SR1.1

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

board/ti/am57xx/mux_data.h

@@ -524,11 +524,11 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
 	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
 	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
 	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
-	{0x074C, 11, 60},	/* CFG_RGMII0_TXCTL_OUT */
-	{0x0758, 7, 120},	/* CFG_RGMII0_TXD0_OUT */
-	{0x0764, 0, 0},		/* CFG_RGMII0_TXD1_OUT */
-	{0x0770, 276, 120},	/* CFG_RGMII0_TXD2_OUT */
-	{0x077C, 440, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x074C, 201, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 229, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 141, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 495, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 660, 120},	/* CFG_RGMII0_TXD3_OUT */
 	{0x0A70, 1551, 115},	/* CFG_VIN2A_D12_OUT */
 	{0x0A7C, 816, 0},	/* CFG_VIN2A_D13_OUT */
 	{0x0A88, 876, 0},	/* CFG_VIN2A_D14_OUT */