Skip to content
Snippets Groups Projects
Commit 722e000c authored by Tom Warren's avatar Tom Warren
Browse files

Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.


Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.

Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
parent 3e8650c0
No related branches found
No related tags found
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment