Skip to content
Snippets Groups Projects
Commit cf839572 authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Nobuhiro Iwamatsu
Browse files

arm: rmobile: lager: Migrate serial driver to drivers model


This adds drivers model support of serial port to Lager board,
and migrate serial port to drivers model.

Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent 9d86e48e
No related branches found
No related tags found
No related merge requests found
...@@ -11,6 +11,8 @@ ...@@ -11,6 +11,8 @@
#include <common.h> #include <common.h>
#include <malloc.h> #include <malloc.h>
#include <netdev.h> #include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/io.h> #include <asm/io.h>
...@@ -189,3 +191,15 @@ void reset_cpu(ulong addr) ...@@ -189,3 +191,15 @@ void reset_cpu(ulong addr)
val |= 0x02; val |= 0x02;
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
} }
static const struct sh_serial_platdata serial_platdata = {
.base = SCIF0_BASE,
.type = PORT_SCIF,
.clk = 14745600,
.clk_mode = EXT_CLK,
};
U_BOOT_DEVICE(lager_serials) = {
.name = "serial_sh",
.platdata = &serial_platdata,
};
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_RMOBILE=y CONFIG_RMOBILE=y
CONFIG_TARGET_LAGER=y CONFIG_TARGET_LAGER=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
...@@ -39,8 +39,6 @@ ...@@ -39,8 +39,6 @@
/* SCIF */ /* SCIF */
#define CONFIG_SCIF_CONSOLE #define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define CONFIG_SCIF_USE_EXT_CLK
/* SPI */ /* SPI */
#define CONFIG_SPI #define CONFIG_SPI
...@@ -83,7 +81,6 @@ ...@@ -83,7 +81,6 @@
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
#define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_TMU_CLK_DIV 4
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment