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  1. Jan 24, 2014
  2. Dec 13, 2013
  3. Nov 04, 2013
  4. Jul 23, 2013
  5. Jun 07, 2013
    • Gabor Juhos's avatar
      pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option · 842033e6
      Gabor Juhos authored
      
      The pci_indirect.c file is always compiled when
      CONFIG_PCI is defined although the indirect PCI
      bridge support is not needed by every board.
      
      Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
      config option and only compile indirect PCI
      bridge support if this options is enabled.
      
      Also add the new option into the configuration
      files of the boards which needs that.
      
      Compile tested for powerpc, x86, arm and nds32.
      MAKEALL results:
      
      powerpc:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 641
        Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
        ----------------------------------------------------------
        Note: the warnings for ELPPC and MPC8323ERDB are present even
        without the actual patch.
      
      x86:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 1
        ----------------------------------------------------------
      
      arm:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 311
        ----------------------------------------------------------
      
      nds32:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 3
        ----------------------------------------------------------
      
      Cc: Tom Rini <trini@ti.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
      Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
      842033e6
  6. Oct 15, 2012
  7. Jul 03, 2012
  8. Jun 20, 2012
  9. Nov 03, 2011
  10. Oct 21, 2011
  11. Oct 05, 2011
  12. Jul 07, 2011
  13. Apr 20, 2011
    • Andy Fleming's avatar
      fsl: Change fsl_phy_enet_if to phy_interface_t · 865ff856
      Andy Fleming authored
      
      The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
      This meant that drivers which used fsl_phy_enet_if to deal with
      PHY interfaces would have to convert between the two (or we would have
      to have them mirror each other, and deal with the ensuing maintenance
      headache). Instead, we switch all clients of fsl_phy_enet_if over to
      phy_interface_t, which should become the standard, anyway.
      
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      Acked-by: default avatarDetlev Zundel <dzu@denx.de>
      865ff856
  14. Oct 26, 2010
    • Wolfgang Denk's avatar
      Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value · 25ddd1fb
      Wolfgang Denk authored
      
      CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
      being able to use "sizeof(struct global_data)" in assembler files.
      Recent experience has shown that manual synchronization is not
      reliable enough.  This patch renames CONFIG_SYS_GBL_DATA_SIZE into
      GENERATED_GBL_DATA_SIZE which gets automatically generated by the
      asm-offsets tool.  In the result, all definitions of this value can be
      deleted from the board config files.  We have to make sure that all
      files that reference such data include the new <asm-offsets.h> file.
      
      No other changes have been done yet, but it is obvious that similar
      changes / simplifications can be done for other, related macro
      definitions as well.
      
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      25ddd1fb
    • Wolfgang Denk's avatar
      Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE · 553f0982
      Wolfgang Denk authored
      
      CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
      some end address; to make the meaning more clear we rename it into
      CONFIG_SYS_INIT_RAM_SIZE
      
      No other code changes are performed in this patch, only minor editing
      of white space (due to the changed length) and the comments was done,
      where noticed.
      
      Note that the code for the PATI and cmi_mpc5xx board configurations
      looks seriously broken.  Last known maintainers on Cc:
      
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      Cc: Denis Peter <d.peter@mpl.ch>
      Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      553f0982
  15. Oct 18, 2010
    • Peter Tyser's avatar
      powerpc: Cleanup BOOTFLAG_* references · d98b0523
      Peter Tyser authored
      
      Now that warm booting is not supported, there isn't a need for the
      BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them.
      
      Note that this change makes the board info bd_bootflags field useless.
      It will always be set to 0, but we leave it around so that we don't
      break the board info structure that some OSes are expecting to be passed
      from U-Boot.
      
      Signed-off-by: default avatarPeter Tyser <ptyser@xes-inc.com>
      d98b0523
    • Wolfgang Denk's avatar
      Makefile: move all Power Architecture boards into boards.cfg · 2ae18241
      Wolfgang Denk authored
      
      Clean up Makefile, and drop a lot of the config.mk files on the way.
      
      We now also automatically pick all boards that are listed in
      boards.cfg (and with all configurations), so we can drop the redundant
      entries from MAKEALL to avoid building these twice.
      
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      2ae18241
    • Wolfgang Denk's avatar
      Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE · 14d0a02a
      Wolfgang Denk authored
      
      The change is currently needed to be able to remove the board
      configuration scripting from the top level Makefile and replace it by
      a simple, table driven script.
      
      Moving this configuration setting into the "CONFIG_*" name space is
      also desirable because it is needed if we ever should move forward to
      a Kconfig driven configuration system.
      
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      14d0a02a
  16. Sep 23, 2010
  17. Aug 09, 2010
  18. Apr 22, 2010
    • Kim Phillips's avatar
      mpc83xx: turn on icache in core initialization to improve u-boot boot time · 1a2e203b
      Kim Phillips authored
      
      before, MPC8349ITX boots u-boot in 4.3sec:
      
              column1 is elapsed time since first message
              column2 is elapsed time since previous message
              column3 is the message
      0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
      0.000 0.000:
      0.000 0.000: Reset Status:
      0.000 0.000:
      0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
      0.032 0.000: Board: Freescale MPC8349E-mITX
      0.032 0.000: UPMA:  Configured for compact flash
      0.032 0.000: I2C:   ready
      0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
      1.516 1.456: FLASH: 16 MB
      2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
      2.652 0.011:         00  10  1095  3114  0180  00
      2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
      2.652 0.000: In:    serial
      2.652 0.000: Out:   serial
      2.652 0.000: Err:   serial
      2.682 0.030: Board revision: 1.0 (PCF8475A)
      3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
      3.080 0.000: TSEC0, TSEC1
      4.300 1.219: IDE:   Bus 0: .** Timeout **
      
      after, MPC8349ITX boots u-boot in 3.0sec:
      
      0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
      0.010 0.000:
      0.010 0.000: Reset Status:
      0.010 0.000:
      0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
      0.017 0.000: Board: Freescale MPC8349E-mITX
      0.038 0.020: UPMA:  Configured for compact flash
      0.038 0.000: I2C:   ready
      0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
      0.260 0.222: FLASH: 16 MB
      1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
      1.390 0.000:         00  10  1095  3114  0180  00
      1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
      1.400 0.010: In:    serial
      1.400 0.000: Out:   serial
      1.400 0.000: Err:   serial
      1.400 0.000: Board revision: 1.0 (PCF8475A)
      1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
      1.832 0.000: TSEC0, TSEC1
      3.038 1.205: IDE:   Bus 0: .** Timeout **
      
      also tested on these boards (albeit with a less accurate
      boottime measurement method):
      
      seconds: before  after
      8349MDS  ~2.6    ~2.2
      8360MDS  ~2.8    ~2.6
      8313RDB  ~2.5    ~2.3 #nand boot
      837xRDB  ~3.1    ~2.3
      
      also tested on an 8323ERDB.
      
      v2: also remove the delayed icache enablement assumption in arch ppc's
      board.c, and add a CONFIG_MPC83xx define in the ITX config file for
      consistency (even though it was already being defined in 83xx'
      config.mk).
      
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
      1a2e203b
    • Kim Phillips's avatar
      mpc83xx: enable command line autocompletion · a059e90e
      Kim Phillips authored
      
      because it's convenient.
      
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
      a059e90e
  19. Feb 22, 2010
  20. Feb 01, 2010
  21. Sep 27, 2009
    • Kim Phillips's avatar
      mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields · c7190f02
      Kim Phillips authored
      
      some LCRR bits are not documented throughout the 83xx family RMs.
      New board porters copying similar board configurations might omit
      setting e.g., DBYP since it was not documented in their SoC's RM.
      
      Prevent them bricking their board by retaining power on reset values
      in bit fields that the board porter doesn't explicitly configure
      via CONFIG_SYS_<registername>_<bitfield> assignments in the board
      config file.
      
      also move LCRR assignment to cpu_init_r[am] to help ensure no
      transactions are being executed via the local bus while CLKDIV is being
      modified.
      
      also start to use i/o accessors.
      
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
      c7190f02
  22. Aug 21, 2009
  23. Jul 27, 2009
  24. Jul 14, 2009
  25. Jun 12, 2009
  26. Mar 30, 2009
  27. Feb 17, 2009
  28. Oct 18, 2008
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