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  1. Sep 02, 2015
  2. Aug 02, 2015
  3. Jun 27, 2015
  4. Jun 08, 2015
  5. May 28, 2015
  6. May 27, 2015
  7. May 26, 2015
  8. May 19, 2015
    • Tim Harvey's avatar
      imx: mx6: add display of CPU temperature grade in print_cpuinfo() · 70caa8e2
      Tim Harvey authored and Stefano Babic's avatar Stefano Babic committed
      
      When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info
      along with the current temperature.
      
      Before:
       CPU:   Temperature 42 C
      
      After:
       CPU:   Automotive temperature grade (-40C to 125C) at 42C
       CPU:   Industrial temperature grade (-40C to 105C) at 42C
       CPU:   Extended Commercial temperature grade (-20C to 105C) at 42C
      
      Cc: Stefan Roese <sr@denx.de>
      Cc: Eric Nelson <eric.nelson@boundarydevices.com>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Jon Nettleton <jon.nettleton@gmail.com>
      Cc: Jason Liu <r64343@freescale.com>
      Cc: Ye Li <b37916@freescale.com>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
      Cc: Markus Niebel <Markus.Niebel@tq-group.com>
      Cc: Peng Fan <b51431@freescale.com>
      Tested-by: default avatarNikolay Dimitrov <picmaster@mail.bg>
      Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
      70caa8e2
    • Tim Harvey's avatar
      imx: mx6: display max cpu frequency in print_cpuinfo() · b83ddac8
      Tim Harvey authored and Stefano Babic's avatar Stefano Babic committed
      
      Display the max CPU frequency as well as the current running CPU frequency
      if the max CPU frequency is available and differs from the current CPU
      frequency.
      
      Before:
      CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
      
      After - using an 800MHz IMX6DL (running at its max)
      CPU:   Freescale i.MX6DL rev1.1 at 792 MHz
      
      After - using a 1GHz IMX6Q (not running at its max):
      CPU:   Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
      
      Cc: Stefan Roese <sr@denx.de>
      Cc: Eric Nelson <eric.nelson@boundarydevices.com>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Jon Nettleton <jon.nettleton@gmail.com>
      Cc: Jason Liu <r64343@freescale.com>
      Cc: Ye Li <b37916@freescale.com>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
      Cc: Markus Niebel <Markus.Niebel@tq-group.com>
      Cc: Peng Fan <b51431@freescale.com>
      Tested-by: default avatarNikolay Dimitrov <picmaster@mail.bg>
      Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
      b83ddac8
    • Prabhakar Kushwaha's avatar
      arm/imx-common: Fix warning 'get_reset_cause' defined but not used · 28420e78
      Prabhakar Kushwaha authored and Stefano Babic's avatar Stefano Babic committed
      
      Fix below warning
      arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but
      not used
       static char *get_reset_cause(void)
      
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      Reviewed-by: default avatarEric Nelson <eric.nelson@boundarydevices.com>
      Acked-by: default avatarStefano Babic <sbabic@denx.de>
      28420e78
  9. May 15, 2015
    • Ulises Cardenas's avatar
      imx: dek_blob: Add explicit include for mapmem · 98a49e53
      Ulises Cardenas authored and Stefano Babic's avatar Stefano Babic committed
      
       Boards such as imx6q_sabresd might not have mapmem.h as part of
       their common library. This causes a build error if the DEK blob
       command is enabled.
      
       Fix: make explicit the include of mapmem.h
      
      Signed-off-by: default avatarUlises Cardenas <Ulises.Cardenas@freescale.com>
      Reviewed-by: default avatarRuchika Gupta <Ruchika.gupta@freescale.com>
      98a49e53
    • Peng Fan's avatar
      i2c: mxc: refactor i2c driver and support dm · 71204e95
      Peng Fan authored
      
      1. Introduce a new structure `struct mxc_i2c_bus`, this structure will
         used for non-DM and DM.
      2. Remove `struct mxc_i2c_regs` structure, but use register offset to access
         registers based on `base` entry of `struct mxc_i2c_bus`.
      3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform
         flags. A new flag is introduced, I2C_QUIRK_FLAG.
      4. Most functions use `struct mxc_i2c_bus` as one of the parameters.
         Make most functions common to DM and non-DM, try to avoid duplicated code.
      5. Support DM, but pinctrl is not included. Pinmux setting is still set
         by setup_i2c, but we do not need bus_i2c_init for DM.
      6. struct i2c_parms and struct sram_data are removed.
      7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist
         paramter of bus_i2c_init is modified to i2c index. Add new prototype
         i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for
         DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus.
         Board file take the responsibility to implement this function, like this:
         "
         int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
         {
      	   if (i2c_bus->index == 0)
      		   force_bus_idle(i2c_pads_info0);
      	   else if (i2c_bus->index == 1)
      		   force_bus_idle(i2c_pads_info1);
      	   else
      		   xxxxxx
         }
         "
      8. Introduce a weak function, enable_i2c_clk
      9. Tested on an i.MX7 platform. Log info:
       => dm tree
       Class       Probed   Name
       ----------------------------------------
       root        [ + ]    root_driver
       simple_bus  [   ]    |-- soc
       simple_bus  [   ]    |   |-- aips-bus@30000000
       simple_bus  [   ]    |   |   |-- anatop@30360000
       simple_bus  [   ]    |   |   `-- snvs@30370000
       simple_bus  [   ]    |   |-- aips-bus@30400000
       simple_bus  [   ]    |   `-- aips-bus@30800000
       i2c         [   ]    |       |-- i2c@30a20000
       i2c         [   ]    |       `-- i2c@30a40000
       simple_bus  [   ]    `-- regulators
       => i2c dev 0
       Setting bus to 0
       => i2c probe
       Valid chip addresses: 08 50
       => i2c md 8 31
       0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08
      
      Signed-off-by: default avatarPeng Fan <Peng.Fan@freescale.com>
      Acked-by: default avatarSimon Glass <sjg@chromium.org>
      71204e95
  10. Apr 23, 2015
  11. Mar 23, 2015
  12. Mar 02, 2015
    • Raul Cardenas's avatar
      imx6: Added DEK blob generator command · 0200020b
      Raul Cardenas authored and Stefano Babic's avatar Stefano Babic committed
      
      Freescale's SEC block has built-in Data Encryption
      Key(DEK) Blob Protocol which provides a method for
      protecting a DEK for non-secure memory storage.
      SEC block protects data in a data structure called
      a Secret Key Blob, which provides both confidentiality
      and integrity protection.
      Every time the blob encapsulation is executed,
      a AES-256 key is randomly generated to encrypt the DEK.
      This key is encrypted with the OTP Secret key
      from SoC. The resulting blob consists of the encrypted
      AES-256 key, the encrypted DEK, and a 16-bit MAC.
      
      During decapsulation, the reverse process is performed
      to get back the original DEK. A caveat to the blob
      decapsulation process,  is that the DEK is decrypted
      in secure-memory and can only be read by FSL SEC HW.
      The DEK is used to decrypt data during encrypted boot.
      
      Commands added
      --------------
        dek_blob - encapsulating DEK as a cryptgraphic blob
      
      Commands Syntax
      ---------------
        dek_blob src dst len
      
          Encapsulate and create blob of a len-bits DEK at
          address src and store the result at address dst.
      
      Signed-off-by: default avatarRaul Cardenas <Ulises.Cardenas@freescale.com>
      Signed-off-by: default avatarNitin Garg <nitin.garg@freescale.com>
      
      Signed-off-by: default avatarUlises Cardenas <ulises.cardenas@freescale.com>
      
      Signed-off-by: default avatarUlises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
      0200020b
  13. Feb 17, 2015
  14. Dec 30, 2014
  15. Dec 01, 2014
  16. Nov 24, 2014
    • Nikita Kiryanov's avatar
      arm: imx: stop sata on boot · 44b9841d
      Nikita Kiryanov authored and Stefano Babic's avatar Stefano Babic committed
      
      Ideally, the Linux kernel should get the hardware in its most
      untouched state. For the most part, U-Boot does not reset the various
      subsystems it touches before boot, and usually Linux deals with it, but
      on some boards (cm_fx6) the Linux kernel fails to detect the ssd
      correctly if sata is used by U-Boot.
      
      Power off sata on OS boot so that Linux will have a clean state to work
      with.
      
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
      Cc: Stefano Babic <sbabic@denx.de>
      44b9841d
  17. Nov 21, 2014
  18. Nov 20, 2014
  19. Nov 13, 2014
  20. Nov 12, 2014
    • Nikita Kiryanov's avatar
      arm: imx: make bmode command work with SPL/U-Boot combo · f2863ff3
      Nikita Kiryanov authored and Stefano Babic's avatar Stefano Babic committed
      
      The bmode command forces the SoC to use a specific boot device
      by writing its boot mode into SRC_GPR9, and notifying the SoC of
      the change using SRC_GPR10[28] bit: if the bit is on, bootROM
      uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
      the boot device.
      
      SPL on the other hand is oblivious to this distinction, so once
      the bootROM loads SPL from the device configured in SRC_GPR10,
      SPL will attempt to load U-Boot from the device configured in
      SRC_SMBR1, which is not updated by the bootROM to the value in
      SRC_GPR9.
      
      The result is that the selected boot device is not used across all
      the boot stages.
      
      Update spl_boot_device() to look at gpr9 when necessary.
      
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Troy Kisky <troy.kisky@boundarydevices.com>
      Cc: Tim Harvey <tharvey@gateworks.com>
      Cc: Eric Nelson <eric.nelson@boundarydevices.com>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Heiko Schocher <hs@denx.de>
      f2863ff3
  21. Nov 03, 2014
    • Ye.Li's avatar
      imx: mx6 sabreauto: Add board support for USB EHCI · 8fe280f3
      Ye.Li authored and Stefano Babic's avatar Stefano Babic committed
      
      On mx6 sabreauto board, there are two USB ports:
      0: OTG
      1: HOST
      The EHCI driver is enabled for this board, but the IOMUX and VBUS power
      control is not implemented, which cause both USB port failed to work.
      This patch fix the problem by adding the board support codes.
      
      Since the power control uses the GPIO pin from port expander MAX7310,
      the PCA953X driver is enabled for accessing the MAX7310.
      
      The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
      its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
      handle GPR register setting.
      
      Signed-off-by: default avatarYe.Li <B37916@freescale.com>
      8fe280f3
    • Ye.Li's avatar
      imx: gpt: Add High frequency clock source support for GPT · 1a1f7950
      Ye.Li authored and Stefano Babic's avatar Stefano Babic committed
      
      Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
      the GPT will select a high frequency clock as clock source.
      Otherwise, the GPT will stay to use 32Khz OSC as clock source.
      
      In the implementation, since only the GPT on i.MX6 series provide the
      clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6
      compile the driver), if the configuration is set, the perclk will be
      selected as clock source.
      MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they
      don't have the 24Mhz OSC clock source option, so also select the perclk
      for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so
      eventually the clock comes from OSC 24Mhz.
      
      Signed-off-by: default avatarYe.Li <B37916@freescale.com>
      1a1f7950
  22. Oct 27, 2014
  23. Oct 25, 2014
  24. Oct 22, 2014
  25. Oct 21, 2014
  26. Aug 20, 2014
    • Marek Vasut's avatar
      ARM: mx6: Prevent overflow in DRAM size detection · fcfdfdd5
      Marek Vasut authored and Stefano Babic's avatar Stefano Babic committed
      
      The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
      only 3840 MiB of that can be really used. In case the controller is
      configured to operate a 4GiB module, the imx_ddr_size() function will
      correctly compute that there is 4GiB of DRAM in the system. Firstly,
      the return value is 32-bit, so the function will effectively return
      zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
      of all that. Thus, clamp the returned size to 3840MiB in such case.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Acked-by: default avatarTim Harvey <tharvey@gateworks.com>
      fcfdfdd5
  27. Jul 23, 2014
  28. Jul 10, 2014
  29. Jun 25, 2014
  30. Jun 06, 2014
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