- Feb 24, 2016
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Qianyu Gong authored
Not only powerpc/mpc85xx but also Freescale Layerscape platforms will use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device tree. So move the function to Fman driver code. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by:
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Prabhakar Kushwaha authored
Before Linux boot DPL must be deployed to DPAA2 interface. So update bootcmd env variable to make sure DPL deployment before Linux boot. Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by:
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Prabhakar Kushwaha authored
Define mcinitcmd env variable to load Management complex during u-boot boot sequence. Signed-off-by:
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Alison Wang authored
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by:
Alison Wang <alison.wang@nxp.com> Reviewed-by:
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Mingkai Hu authored
Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by:
Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by:
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Shengzhou Liu authored
DDR erratum A-009942 applies to LS1043A. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
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Aneesh Bansal authored
PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by:
Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by:
Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by:
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Ruchika Gupta authored
The output ring needs to be invalidated before enqueuing the job to SEC. While allocation of space to output ring, it should be taken care that the size is cacheline size aligned inorder to prevent invalidating valid data. The patch also correct the method of aligning end of structs while flushing caches Since start = align(start_of_struct), it is incorrect to assign end = align(start + struct_size). It should instead be, end = align(start_of_struct + struct_size). Signed-off-by:Saksham Jain <saksham@nxp.com> Signed-off-by:
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Ashish Kumar authored
Increase default hugepage count to 256 from 16 Signed-off-by:
Ashish Kumar <Ashish.Kumar@freescale.com> Reviewed-by:
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York Sun authored
Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart to driver model suport. Enable lpuart port driver. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
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- Feb 23, 2016
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York Sun authored
Split duart configuration as device tree file. Move /chosen node out of board commone device tree. Convert ls1021aqds nor and SD configurations to driver model support (qspi already uses DM). Enable ns16550 DM serial driver for nor configurations. Signed-off-by:
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- Feb 21, 2016
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git://www.denx.de/git/u-boot-imxTom Rini authored
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In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals affected by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is to set the peripherals to Domain0 by A core, since A core in Domain0. The peripherals which will be used by M4, will be set to Domain1 by M4. For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will set WDOG4 to domain1, because M4 will use WDOG4. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1. This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0. Signed-off-by:
Ye.Li <ye.li@nxp.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Introduce macros and command to support booting M4 core for i.MX7D SabreSD board. Signed-off-by:
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Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by:
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Introduce macros and command to support booting M4 core for i.MX6SX SabreSD board. Signed-off-by:
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Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by:
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To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000". Introduce Kconfig option IMX_BOOTAUX. Signed-off-by:
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If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE. Signed-off-by: -
Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Signed-off-by:
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Add the definitions for the RDC mappings for i.MX6 SoloX. Signed-off-by:
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Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains. Signed-off-by:
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Introudce rdc regs structure and rdc sema reg structure for i.MX6. For now, to i.MX6, only i.MX6SX supports this. Signed-off-by:
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Add board_mmc_getcd function and declare CD_GPIO for SDCard. Signed-off-by:Julien Corjon <corjon.j@ecagroup.com>
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Specify max_bus_width directly in usdhc_cfg static definition instead of tweaking it in the board_mmc_init() function. Signed-off-by: -
USDHC2 does not exist on mx6quq7 board, as USDHC4 was already been declared this is probably a typo. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com>
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Implement board specific functions to select the environment device and partition when booting from SD/MMC. SD2: mmc 0 0 SD3: mmc 1 0 eMMC: mmc 2 1 Signed-off-by:Soeren Moch <smoch@web.de>
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commit 216d286c [imx: mx6: implement mmc_get_env_dev] introduced selection of the environment device according to the boot device when booting from SD/MMC. Extend this functionality for also selecting the device partition. Signed-off-by:
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Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: -
Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by:
Ulises Cardenas <raul.casas@nxp.com> Reviewed-by:
Stefano Babic <sbabic@denx.de>
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When running the 'ums' command we get: => ums 0 mmc 0 UMS: disk start sector: 0x0, count: 0xe18000 g_dnl_register: failed!, error: -22 ERROR: g_dnl_register failed at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage() Fix this by initializing USB OTG1 port as USB device mode instead of host. Signed-off-by:Fabio Estevam <fabio.estevam@nxp.com>
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Use the new NXP email address for the board maintainer. Signed-off-by: -
Select CONFIG_FSL_QSPI so that the SPI can be probed: => sf probe SF: Detected N25Q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB Signed-off-by:
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Commit 276d3ebb removed htole32() but missed to remove the corresponding header. This is annoying, since BSD systems do not have endian.h. Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com> Acked-by:
Marek Vasut <marex@denx.de> Acked-by:
Michael Heimpold <mhei@heimpold.de>
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Bin Meng authored
Update existing documentation to mention Intel Bayley Bay board instructions, an additional Bay Trail based board to MinnowMax. This also adds a minor change to QEMU section to indicate clearly the instructions are for bare mode. Signed-off-by:
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Bin Meng authored
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by:
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Bin Meng authored
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by:
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Bin Meng authored
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by:
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