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  1. May 05, 2015
  2. Feb 06, 2015
    • Stefan Roese's avatar
      arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr · f8d25d74
      Stefan Roese authored
      
      This patch adds the DDR3 setup and training code taken from the Marvell
      U-Boot repository. This code used to be included as a binary (bin_hdr)
      into the AXP boot image. Not linked with the main U-Boot. With this code
      addition and the following serdes/PHY setup code, the Armada-XP support
      in mainline U-Boot is finally self-contained. So the complete image
      for booting can be built from mainline U-Boot. Without any additional
      external inclusion. Hopefully other MVEBU SoC's will follow here.
      
      Support for some SoC's has been removed in this version. This is:
      
      MV_MSYS:
      The code referred to by the MV_MSYS define is currently unused. And its
      not really planned to support this in mainline. So lets remove it to
      make the code clearer and increase the readability.
      
      MV88F68XX (A38x):
      The code referred to by the MV88F68XX define (A38x) is currently unused.
      And its partial and not sufficient for this device in this stage.
      So lets remove it to make the code clearer and increase the readability.
      
      MV88F66XX (ALP):
      The code referred to by the MV88F66XX define is currently unused. And its
      not really planned to support this in mainline. So lets remove it to
      make the code clearer and increase the readability.
      
      MV88F78X60_Z1:
      The code referred to by the MV88F78X60_Z1 define is currently unused. As the
      Z1 revision of the AXP is not supported in mainline anymore.
      So lets remove it to make the code clearer and increase the readability.
      
      Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
      is B0 and this is the only one that is actively supported in this code
      version.
      
      Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
      on a custom fixed DDR configuration board (maxbcm).
      
      Note:
      This code has undergone many hours of coding-style cleanup and refactoring.
      It still is not checkpatch clean though, I'm afraid. As the factoring of the
      code has so many levels of indentation that many lines are longer than 80
      chars. This might be some task to tackly later on.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Reviewed-by: default avatarLuka Perkov <luka.perkov@sartura.hr>
      f8d25d74
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