- Sep 01, 2012
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Bo Shen authored
Add at91sam9x5 series spi flash boot support Using at91sam9x5ek_spiflash to configure, then it can boot from at25df321 serial flash SPI mater work in 30Mhz speed, while not 1Mhz speed. This will base on atmel_spi patch, or else, it will occur receive overrun Signed-off-by:
Bo Shen <voice.shen@atmel.com> Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Bo Shen authored
Remove CONFIG_ARCH_CPU_INIT for at91sam9g10ek and at91sam9m10g45ek Signed-off-by:
Bo Shen <voice.shen@atmel.com> [rebase on TOT] Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Andreas Bießmann authored
A lot of at91 boards have the console_init_f in board_init. This is useless cause it was called before by generic code in lib/board.c. Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com> cc: Jens Scharsig <esw@bus-elektronik.de> cc: Stelian Pop <stelian@popies.net> cc: Sedji Gaouaou<sedji.gaouaou@atmel.com> cc: Albin Tonnerre <albin.tonnerre@free-electrons.com> cc: Eric Benard <eric@eukrea.com> Tested-by:
<voice.shen@atmel.com> Tested-by:
<voice.shen@atmel.com> Acked-by:
Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Tested-by:
Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
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Andreas Bießmann authored
Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com> cc: Stelian Pop <stelian@popies.net>
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Bo Shen authored
The atmel at91sam9x5 series spi has feature to avoid receive overren Using the patch to enable it Signed-off-by:
Bo Shen <voice.shen@atmel.com> Acked-by:
Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Bo Shen authored
Fix the name error Signed-off-by:
Bo Shen <voice.shen@atmel.com> Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Bo Shen authored
As the maintainer for at91sam9g10ek and at91sam9m10g45ek can not reach any more. So I wish to take over the maintainer for sam9g10 and sam9m10g45 Signed-off-by:
Bo Shen <voice.shen@atmel.com> Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Bo Shen authored
fix a bug: when not boot from NAND, the NAND flash can not be detected. Using this to fix it Signed-off-by:
Bo Shen <voice.shen@atmel.com> Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Xu, Hong authored
Before reset dbgu transmitter, we just wait TXEMPTY to drain the transmitter register(Just in case). If not doing this, we may sometimes see several weird characters from DBGU. A short delay is also added to make sure the new serial settings are settled. Signed-off-by:
Hong Xu <hong.xu@atmel.com> [cherry-picked from u-boot-atmel/old-next] Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Andreas Bießmann authored
The old update script uses 'load_addr' which is never set. Use 'fileaddr' instead which is automagically set by e.g. dhcp. Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com> cc: Stelian Pop <stelian@popies.net>
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Bo Shen authored
Remove CONFIG_ARCH_CPU_INIT, no need it anymore Signed-off-by:
Bo Shen <voice.shen@atmel.com> Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com>
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Benoît Thébaudeau authored
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
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Benoît Thébaudeau authored
Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
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Stefano Babic authored
The macro to get the gpio number id was renamed to IMX_GPIO_NR as in kernel. Fix the wrong name in efika. Signed-off-by:
Stefano Babic <sbabic@denx.de> CC: Matt Sealey <matt@genesi-usa.com> Acked-by:
Matt Sealey <matt@genesi-usa.com>
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Ashok Kumar Reddy authored
Signed-off-by:
Ashok Kumar Reddy <ashokkourla2000@gmail.com>
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Matt Sealey authored
We have no idea where the DCD was derived from for Smartbook support, but they differ from the Smarttop settings, MX51EVK settings and certainly don't correspond to any shipped or development version of U-Boot that Genesi has ever had on any Smartbook. So, copy the calibrated, verified settings from the U-Boot as shipped with every Smartbook since retail production. Remove those few settings that just set the POR defaults which have already been confirmed for the previous Smarttop DCD change. One of the lines is specific to i.MX51 TO3 designs and therefore TO2 Smartbooks will possibly not work so reliably with this new DCD; that said, TO2 Smartbooks basically don't exist at retail and the number of units in the world is less than 5 (3 of which are at the Genesi office or owned by Genesi employees). Many hours of memory testing confirms the new settings are stable. Patch v2: * picked the correct commit from our development tree, correcting tuned DDR ODF setting (which was correct anyway) Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de>
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Matt Sealey authored
This is a rework of a previously submitted patchset and bundles the main board support and USB support into a single commit. It requires the patch "mx5: add iomux-mx51.h include" * Use iomux-mx51.h include to simplify board configuration. * Simplify LED support (remove efikamx_toggle_led, change lit LEDs). * Simplify MMC support for CD and WP pin differences. * Fix broken CPU voltage setting - comment said 1.1V but the code set to 1.2V. It should never have been set to 1.2V even on i.MX51 TO2 and all available Linux kernels would drop the voltage to 1.1V anyway and work reliably. This should lower power consumption during the boot process. * Function renames for readability. * Some board identification string changes to match actual product names. * Passes checkpatch (v2) Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Cc: Stefano Babic <sbabic@denx.de>
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fabio.estevam@freescale.com authored
For representing a timeout value, it makes more sense to pass it as 'unsigned int'. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
Marek Vasut <marex@denx.de> Acked-by:
Stefano Babic <sbabic@denx.de>
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Matt Sealey authored
Update maintainer for "efikamx" and "efikasb" to myself. Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de>
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Matt Sealey authored
PCBID pads seem to need time to settle due to external pulldowns, otherwise we are reading floating GPIO pins with implicit pad pullups and get the wrong data. However we can't "wait" at the time we need them before relocation, since timers are not available. The time taken to get from DCD to the code requiring the pads set seems to be more than long enough (even with caches enabled). We have space in the DCD due to the DDR settings changes to configure all the pad settings we need for this, plus the LED pad settings too which reduces the amount of code required later on. Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Acked-by:
Stefano Babic <sbabic@denx.de>
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Matt Sealey authored
Efika MX boards configure their DDR pad settings twice, one in the DCD generated from imximage_*.cfg and again in init_drive_strength called before relocation. Rather than doing this, roll the changes it makes into the DCD so DDR is set up before a single line of code in U-Boot is run. The settings are identical with this DCD block which is shorter (by 7 entries) than the old one, and after the output of init_drive_strength since a lot of the functionality in the existing DCD and init_drive_strength function was just setting the POR defaults. This goes to explain some now-missing entries. Several hundred rounds of mtest have been run to test the settings before and after to confirm DDR is stable and no ill-effects have been found. Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Acked-by:
Stefano Babic <sbabic@denx.de>
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Matt Sealey authored
* Move Efika MX Smarttop and Smartbook boards into a "genesi" vendor directory * Rename efikamx -> mx51_efikamx since there is an mx53_efikamx and mx6_efikamx to come Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Acked-by:
Stefano Babic <sbabic@denx.de> Acked-by:
Stefano Babic <sbabic@denx.de>
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Marek Vasut authored
Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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Marek Vasut authored
Align the SSP clock speed with oscilator to achieve higher transfer stability. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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Marek Vasut authored
This change implements DMA chaining into SPI driver. This allows the transfers to go much faster, while also fixing SF issues. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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Marek Vasut authored
Load from SPI flash can create a long DMA chain, which can take long time to transfer. Change the DMA timeout to roughly 10s to prevent such long chains misreporting errors. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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Marek Vasut authored
Align this structure to DMA alignment size. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
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Ashok Kumar Reddy authored
Signed-off-by:
Ashok Kumar Reddy <ashokkourla2000@gmail.com> Acked-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
Stefano Babic <sbabic@denx.de>
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trem authored
Signed-off-by:
Philippe Reynes <tremyfr@yahoo.fr> Acked-by:
Stefano Babic <sbabic@denx.de>
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trem authored
The gpio api has been tested on an armadeus apf27. Signed-off-by:
Philippe Reynes <tremyfr@yahoo.fr> Acked-by:
Stefano Babic <sbabic@denx.de>
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Matt Sealey authored
Allow usage of the imx-common/iomux-v3.h framework by including pad settings for the i.MX51. The content of the file is taken from Linux kernel at commit 5d23b39 plus the required changes to make it work in U-Boot. The contained pad settings are the minimum required to make an Efika MX boot and get all the currently-implemented peripherals working in U-Boot. It is recommended that this file not be just a dumping ground for pins but only contain the settings required for all the boards using it. Changes for v2: * reference commit id from Linux kernel * additionally roll in the USB pads * removed GPIO_NUMBER define Signed-off-by:
Matt Sealey <matt@genesi-usa.com> Acked-by:
Stefano Babic <sbabic@denx.de>
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Otavio Salvador authored
The DRAM initialization, after SPL has complete, is exactly the same for all mxs SoCs so we should name it accordinly. The following boards has been changed: * apx4devkit * m28evk * mx28evk * sc_sps_1 Signed-off-by:
Otavio Salvador <otavio@ossystems.com.br> Acked-by:
Marek Vasut <marex@denx.de> Acked-by:
Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
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Otavio Salvador authored
The internal Ethernet controller is only available on i.MX28 processors so it needs to use CONFIG_MX28 guardian to avoid having this code called in others. Signed-off-by:
Otavio Salvador <otavio@ossystems.com.br> Acked-by:
Marek Vasut <marex@denx.de>
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Otavio Salvador authored
All other header are going to use i.MX23 so we change this for consistency. Signed-off-by:
Otavio Salvador <otavio@ossystems.com.br>
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Benoît Thébaudeau authored
gpio_get_value() should use PSR like Linux, not DR, because DR does not always reflect the pin state, while PSR does. This is especially useful to detect a short circuit on a GPIO pin configured as output, or to read the level of a pin controlled by a non-GPIO IOMUX function. Signed-off-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by:
Stefano Babic <sbabic@denx.de>
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Fabio Estevam authored
Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com>
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Fabio Estevam authored
Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com>
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Fabio Estevam authored
Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com>
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Benoît Thébaudeau authored
Signed-off-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by:
Stefano Babic <sbabic@denx.de>
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Benoît Thébaudeau authored
Signed-off-by:
Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by:
Stefano Babic <sbabic@denx.de>
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