- Dec 22, 2020
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Maximilian Adducchio authored
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- Dec 16, 2020
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Maximilian Adducchio authored
* correct Fallback boot decision by reading sys_active file * itest.w *${loadaddr} == 0x4241 is true when sys_active contains "AB" -> results in Fallback to root_B * itest.w *${loadaddr} == 0x4142 is true when sys_active contains "BA" -> resultds in Fallback to root_A -
Maximilian Adducchio authored
configs/kontron_mx6ul_defconfig: set CONFIG_ENV_OVERWRITE (allow overwriting of mac via environment)
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Maximilian Adducchio authored
* correct NOR SPI U-Boot offset (128k) * set sf default speed to 10Mhz
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- Dec 15, 2020
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Maximilian Adducchio authored
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Maximilian Adducchio authored
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- Dec 11, 2020
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Maximilian Adducchio authored
* set CONFIG_BOOTCOUNT_BOOTLIMIT=3
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Maximilian Adducchio authored
* working revision of A / B Boot environment * this still has to be tested
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- Dec 07, 2020
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Frieder Schrempf authoredSimilar as in bc9b2bd1 for the display detection, we are using the wrong I2C port for detecting the old PMIC in order to print the deprecation warning. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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- Oct 08, 2020
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Maximilian Adducchio authored
mx8mm/spl.c in function do_board_detect: scan on i2c bus 1 for address 0x5d (goodix touchcontroller)
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- Oct 06, 2020
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Frieder Schrempf authored
Signed-off-by: -
Frieder Schrempf authored
Signed-off-by: -
Frieder Schrempf authored
If less than 8G is available on the board, we detect it at runtime. Signed-off-by: -
Frieder Schrempf authored
We backported support for a common dram_init() in the soc.c file. Let's use it. Signed-off-by: -
Frieder Schrempf authored
If we want to detect DDR sizes up to 8G at runtime, we need to set PHYS_SDRAM_SIZE and PHYS_SDRAM_2_SIZE to their maximums of 3G and 5G respectively. In case there is actually only 4G of RAM available, we need to calculate the correct sizes for bank 1 and 2. This method works if board_phys_sdram_size() is defined to return the actual RAM size accross both banks by calling get_ram_size(). Signed-off-by:
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- Oct 05, 2020
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the mem_map structure containing the size of SDRAM is used in various cache functions in cache_v8.c thus we need to update it with the sdram size the board is configured with as well. Without this the cache functions do not get setup properly and can hang in the case where a board reports more SDRAM than defined in PHYS_SDRAM_SIZE. Signed-off-by:Tim Harvey <tharvey@gateworks.com>
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Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank. When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue. Signed-off-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> Tested-by:
Peng Fan <peng.fan@nxp.com>
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- Oct 01, 2020
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Frieder Schrempf authored
The preferred property to pass the MAC address to the kernel is local-mac-address. Only use mac-address as a fallback. Signed-off-by:
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- Sep 10, 2020
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Frieder Schrempf authored
For rev0 of the SoM we had a very small batch with a 2GB RAM from some vendor. We don't produce these anymore and now use DDR from Micron with 1/2/4GB. As it makes things easier drop support for the old DDR and add support for the 4GB type instead. Signed-off-by: -
Frieder Schrempf authored
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- Sep 08, 2020
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Frieder Schrempf authored
With the current devicetrees from Linux ethernet didn't work for some reason. Disable the second ethernet and let the first one control MDIO to make it work in U-Boot. Signed-off-by:
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- Sep 01, 2020
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The 'selfref_en' should be bit'0', so correct the setting to enable the auto self-refresh. Reviewed-by:
Jian Li <jian.li@nxp.com> Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Signed-off-by:
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Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by:
Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by:
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Frieder Schrempf authored
On some SoMs we have a 2GB Micron RAM chip. Update the parameters to be able to detect it correctly. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
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- Jul 23, 2020
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Frieder Schrempf authored
Change the message about the board type printed by SPL to match what we have for i.MX8MM. Signed-off-by: -
Frieder Schrempf authored
This simplifies and cleans the configuration for the Kontron i.MX8MM SoMs and boards. We adjust the devicetrees to reflect the changes that were made in the kernel. We also drop the support for the outdated rev0 boards. Signed-off-by: -
This patch synchronizes the device tree with that from 5.6.7. This also adds nodes for crypto and ddrc, which makes keeping the device tree files from individual boards in sync with the Linux kernel. This is helpful when boads reference those nodes. Signed-off-by:Adam Ford <aford173@gmail.com>
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- Jul 08, 2020
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Frieder Schrempf authored
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Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by:
Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com>
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The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by:
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Toshiba recently launched new revisions of their serial SLC NAND series. TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements. Basic parameters are same so lets add support for this new revision. Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ Signed-off-by:
Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by:
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- Jun 09, 2020
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The default boot fuse settings use the SD card (MMC1) as primary boot device, but allow SPI NOR as a fallback boot device. We cannot use the SPI NOR as primary boot otherwise we may mix the SPL (from the MMC1) and U-Boot proper from the SPI NOR. Also if no U-Boot image is flashed to SPI NOR, the boot will be interrupted as the SPI NOR access is blocking the second boot device (MMC). If booting for MMC we should use the U-Boot proper from MMC as first try and SPI NOR only second. Signed-off-by:
Otavio Salvador <otavio@ossystems.com.br> [Adjust comment/commit message and refactor code] Signed-off-by:
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- Jun 08, 2020
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Frieder Schrempf authored
This reverts commit 3d58441a. We can't always use the SPI NOR as first boot device, as this breaks the case when we boot from SD-card and the SPI NOR boot is tried first and blocking the other boot devices. This is probably the case because there's currently no way to detect if the SPI NOR is available (can be probed), but doesn't have valid bootable content flashed!? Signed-off-by:
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- Jun 03, 2020
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Frieder Schrempf authored
The default boot fuse settings use the SD card (MMC1) as primary boot device, but allow SPI NOR as a fallback boot device. We can't detect the fallback case and spl_boot_device() will return BOOT_DEVICE_MMC1 despite the actual boot device beeing SPI NOR. Therefore we provide a custom boot order to probe the SPI NOR first. Signed-off-by: -
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We need to use BUS 1 during SPL as it still does not use the driver model for using the device alias. Signed-off-by:
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- May 26, 2020
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Same as the upstream fix for building dtc with gcc 10. Upstream-Status: Backport [2020.04] Signed-off-by:
Peter Robinson <pbrobinson@gmail.com> (cherry picked from commit 018921ee)
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