- Sep 06, 2016
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Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Eric Nelson <eric@nelint.com>
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- Nov 12, 2015
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There is really no need to provide an empty reset_cpu() implementation, so just remove it. Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
Christian Gmeiner <christian.gmeiner@gmail.com>
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- Sep 13, 2015
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We should not return 0 on failure, so return a negative error code instead. Also centralize the error path so that is easier to follow. Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: -
Remove duplicated SYS_SOC Kconfig entry from board Kconfig, because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig. Signed-off-by:
Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: "Eric Bénard" <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Marek Vasut <marex@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Acked-by:
Stefan Roese <sr@denx.de> Acked-by:
Marek Vasut <marex@denx.de> Acked-by:
Markus Niebel <Markus.Niebel@tq-group.com> Acked-by:
Troy Kisky <troy.kisky@boundarydevices.com> Acked-by:
Igor Grinberg <grinberg@compulab.co.il>
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- Jun 08, 2015
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On this bus there is a EEPROM containing EDID and ddr3 calibration information. Signed-off-by: -
Make it possible to use the i2c bus in SPL. Signed-off-by:
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- Jan 22, 2015
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Currently we only support the Micron MT41K128M16JT-125 ddr3 chip. Signed-off-by: -
Signed-off-by: -
We need this way for SPL boot. Signed-off-by: -
To support different ddr3 memory sizes we should start using imx_ddr_size(..) instead of the define PHYS_SDRAM_SIZE. Signed-off-by:
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- Nov 24, 2014
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When an invalid USDHC port is passed we should return -EINVAL instead of 0. Also, return the error immediately on fsl_esdhc_initialize() failure. Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by:
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- Nov 13, 2014
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Today I got the final board and found out that a different connector is used as the one on my development board. The new connector has swaped pins for cd and wp. This change is tested on a production ready board. Signed-off-by:
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- Oct 30, 2014
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Signed-off-by: -
On the 'mr' variant switching to 'mmc dev 1' will result in "MMC: no card present". Signed-off-by: -
The older 'mr' variant and the generic variant of the OT1200 differ in some places. As the name suggests the generic variant supports more boot devices. In order to be compatible with the 'mr' variant we define some 'feature' GPIOs. On the 'mr' variant this pads are not connected so we define their state with the help of the internal pullups. On the generic variant this GPIOs are connected and represent the state of the hardware. Signed-off-by:
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- Oct 29, 2014
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Georges Savoundararadj authored
This commit introduces a Kconfig symbol for each ARM CPU: CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136, CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100. Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected for CPU_ARM1176 and CPU_V7. For each target, the corresponding CPU is selected and the definition of SYS_CPU in the corresponding Kconfig file is removed. Also, it removes redundant "string" type in some Kconfig files. Signed-off-by:
Georges Savoundararadj <savoundg@gmail.com> Acked-by:
Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
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- Oct 23, 2014
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One of the possible boot devices can be sata. Signed-off-by: -
Commit 155fa9af changed the way to define a GPIO line, which can be used to force CS high across multiple transactions. In order to fix sf detection change board code to make use of board_spi_cs_gpio(..). Signed-off-by:
Stefano Babic <sbabic@denx.de> Acked-by:
Nikita Kiryanov <nikita@compulab.co.il>
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- Oct 21, 2014
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Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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- Oct 06, 2014
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This patch adds support for the OT1200 series of devices. Following components are used in u-boot: + ethernet + i2c + emmc + gpio For more details see README. Changes v1 > v2 - make use of enable_cspi_clock(..) - fix usage of OUTPUT_40OHM define - added README Changes v2 > v3 - improve spelling in README - added own copy of mx6q_4x_mt41j128.cfg Signed-off-by:
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