- May 15, 2012
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Simon Glass authored
We need to iterate through subnodes of a parent, looking only at compatible nodes. Add a utility function to do this for us. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
fdtdec_locate_array() locates an integer array but does not copy it. This saves the caller having to allocated wasted space. Access to array elements should be through the fdt32_to_cpu() macro. Signed-off-by:
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Marek Vasut authored
Do not define serial_putc() and serial_puts() calls if CONFIG_SPL_SERIAL_SUPPORT is set. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by:
Stefano Babic <sbabic@denx.de>
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Marek Vasut authored
If the WP function is NULL, simply assume the card is always RW. Signed-off-by:
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Marek Vasut authored
Signed-off-by:Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
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Marek Vasut authored
Signed-off-by: -
Marek Vasut authored
This code is part of battery boot support for i.MX28. Signed-off-by: -
Marek Vasut authored
Signed-off-by: -
Marek Vasut authored
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF data pins interferes with the BootROM's boot mode sampling. So shut the controller down. Signed-off-by: -
Marek Vasut authored
Signed-off-by: -
Marek Vasut authored
This patch implements code that samples i.MX28 boot pads and reports boot mode accordingly. Signed-off-by: -
Marek Vasut authored
Pass memory size from SPL via structure located in SRAM instead of SCRATCH registers. This allows passing more data about boot from SPL to U-Boot, like the boot mode pads configuration. Signed-off-by: -
Marek Vasut authored
Add "update_sd_firmware" command to easily reload the SD card of m28evk kit. This comes handy when the board boots from SD card. Signed-off-by: -
Marek Vasut authored
Signed-off-by: -
Marek Vasut authored
Abstract out common register setup. This also configured r_cntrl to correct value at registration time. Signed-off-by: -
Stefano Babic authored
After an update to the MX51 reference manual (Rev. 5), the values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH are now clearly wrong: "Bit 13: High / Low Output Voltage Range. This bit selects the output voltage mode for SD2_CMD. 0 High output voltage mode 1 Low output voltage mode" The values are currently negated in code - fixed. Reported-by:
David Jander <david.jander@protonic.nl> Signed-off-by:
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Marek Vasut authored
This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by:
Detlev Zundel <dzu@denx.de>
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Fabio Estevam authored
MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2. Currently only SS0 is supported in the mxs_spi driver. Allow all the three chip select to work by selecting the desired one in bits 20 and 21 of the HW_SSP_CTRL0 register. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Acked-by:
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Fabio Estevam authored
Introduce spi_cs_is_valid() for validating spi bus and chip select numbers. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Fabio Estevam authored
There is no need to set the VBUS power enable to 0 first and then to 1. Set it to 1 in the gpio_direction_output() function. While at it, use the standard naming convention for the GPIO comment. Signed-off-by: -
Fabio Estevam authored
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by:
Yu Li <yk@magniel.com> Signed-off-by:
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Fabio Estevam authored
On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator so that the mx53 USBH1 PHY receives the 3.3V voltage. Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the commands: usb start usb info ,which correctly detected and printed the USB pen drive information. Signed-off-by:
Jason Liu <r64343@freescale.com> Acked-by:
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Fabio Estevam authored
Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz. Signed-off-by:
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Fabio Estevam authored
As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC, we need to be able to build both drivers. Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present. Signed-off-by:
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Timo Ketola authored
Signed-off-by:
Timo Ketola <timo@exertus.fi> Acked-by:
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Timo Ketola authored
types.h must be included in imx-regs.h if one wants to include imx-regs.h in a board configuration file. That for one's part is necessary, if one wants to use addresses defined in imx-regs.h. For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and a proper thing is to define it with IMX_MMC_SDHCx_BASE in board configuration file. This patch fixes the build in that case. Signed-off-by:
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Timo Ketola authored
The reference manual of i.MX25 (nor i.MX31) does not define such register. This seems to access read only UH2_CAPLENGTH register (if CONFIG_MXC_USB_PORT is zero). Signed-off-by:
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Timo Ketola authored
The USB controller in i.MX25 has a PORTSCx registers which should be set. In this regard it is similar to the controller in i.MX31. As this file is compiled only with i.MX25 and -31, #ifdef check can be removed. Signed-off-by:
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Timo Ketola authored
Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Timo Ketola authored
Signed-off-by:
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Timo Ketola authored
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere. Signed-off-by:
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Eric Nelson authored
Signed-off-by:
Eric Nelson <eric.nelson@boundarydevices.com> Acked-by:
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Eric Nelson authored
Signed-off-by:
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Dirk Behme authored
Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by:Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com>
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Lauri Hintsala authored
NAND support is not enabled by default because Eval Kit is not delivered with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config. Signed-off-by:
Lauri Hintsala <lauri.hintsala@bluegiga.com> Acked-by:
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Wolfgang Grandegger authored
To get USB working again on the i.MX6, this patch fixes a bug introduced with commit 522b2a02 "Add proper IO accessors for mx6 usb registers.". At that occasion, I also added the missing __iomem directive. Cc: Marek Vasut <marex@denx.de> CC: Fabio Estevam <festevam@gmail.com> Signed-off-by:
Wolfgang Grandegger <wg@denx.de>
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Marek Vasut authored
Signed-off-by: -
Marek Vasut authored
This reverts commit 69d26d09. Apparently, this commit got mainline only because of out-of-tree port and causes breakage on board that is mainline. Revert. Reason: * The OOT board has 512MB of DRAM, enabling this additional address line enabled it to work fine with 512MB of RAM. * Every mainline port has max. 256MB of DRAM, therefore this revert has no impact on any mainline port * Though this caused a problem with new M28 board with 256MB of DRAM where the chips are wired differently. The patch-to-be-reverted caused the DRAM to behave like this: [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again] Therefore to retain the current one-memory-init-rules-them-all situation, revert this patch until another board emerges and will actually be pushed mainline that needs different setup. Signed-off-by:
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Marek Vasut authored
This will eventually be needed with Linux 3.5, which will be the point when MXS will be switched to FDT. Signed-off-by: -
Fabio Estevam authored
There are two types of mx53loco boards: initial boards were built with a Dialog DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC. Add DA9053 PMIC support and adjust the required voltages and clocks for running the CPU at 1GHz. Tested on both versions of mx53loco boards. In the case of a MC34708-based board the CPU operating voltage remains at 800MHz. Signed-off-by:
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