- Dec 19, 2014
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Bin Meng authored
Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Bin Meng authored
Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Bin Meng authored
Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Acked-by:
Simon Glass <sjg@chromium.org>
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- Nov 25, 2014
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Simon Glass authored
Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable this so that it can be used instead of native execution if desired. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Now that we have the required drivers, enable video support with a suitable option ROM. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable SPI so that the SPI flash can be used. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable USB support on link - there are two EHCI ports available. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add the requires settings to enable SATA on link. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable this option so that we can configure the available PCI devices. Also make sure that PCI is available early after relocation as we use it for several other subsystems. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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- Nov 21, 2014
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Simon Glass authored
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically. Unfortunately it relies on binary blobs so we cannot require this for the default build as yet. Create a u-boot.rom output file for this purpose. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by:
Simon Glass <sjg@chromium.org>
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