Since 1.0 and 2.0 use different snum table,
we fixup the snum value according to SPRN_SVR.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The real clock divider is 4 times of the bits LCRR[CLKDIV],
according the latest RevF RM.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS.

Signed-off-by: Jin Qing <B24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This reverts commit bc20f9a9.

The original code was correct.  I clearly need glasses or a brown
paper bag.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits
instead of 4.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Commit b5b004ad caused the sector_size to
be calculated incorrectly when the part size was not hardcoded.  This is
because the new code relied on part->size but tried to do the calculation
before it was initialized properly, and it did not take into consideration
the magic SIZE_REMAINING define.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

At least on OS X 10.5 and older, getline does not exist.  So split out the
function from the mingw code so that we can pull it in for Darwin systems.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The current libfdt object rules hard depend implicitly on the .depend file
being correct.  If it isn't, then it is unable to properly compile the
objects.  Give it a full path like all the other implicit rules here so it
will always work in face of .depend issues.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

If you really want to slim down U-Boot and you would rather use a higher
compression scheme (like LZMA), it'd be nice to disable gzip/zlib since
these code bases take up a significant amount of space.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

This patch adds support for "imximage" (MX Boot Image)
to the mkimage utility. The imximage is used on the Freescales's
MX.25, MX.35 and MX.51 processors.

Further details under doc/README.imximage.

This patch was tested on a Freescale mx51evk board.

Signed-off-by: Stefano Babic <sbabic@denx.de>

Signed-off-by: Detlev Zundel <dzu@denx.de>

Content of the RSR is put into gd early so we can output it together
with the CPU info.  The clearing of gd in board_init_f is redundant for
this architecture as it is done in cpu_init_f so we remove it.

Signed-off-by: Detlev Zundel <dzu@denx.de>

Normally the processor clock has a divisor of 2.
In some cases this this needs to be set to 4.
Check the user has set environment mdiv to 4 to change the divisor.

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>

SPEAr320 SoC support contains basic spear320 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
- emi driver(cfi support)

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr310 SoC support contains basic spear310 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
- emi driver(cfi support)

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP

The standard CFI driver is used to interface with NOR flashes

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr300 SoC support contains basic spear300 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver

Signed-off-by: Vipin <vipin.kumar@st.com>

This patch adds the  support to read and write mac id from i2c
memory.
For reading:
	if (env contains ethaddr)
		pick env ethaddr
	else
		pick ethaddr from i2c memory
For writing:
	chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id
	in i2c memory

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr600 SoC support contains basic spear600 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr SoCs contain a synopsys usb device controller.
USB Device IP can work in 2 modes
- DMA mode
- Slave mode

The driver adds support only for slave mode operation of usb
device IP. This driver is used along with standard USBTTY
driver to obtain a tty interface over USB on the host

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr SoCs contain a synopsys i2c controller.
This patch adds the driver for this IP.

Signed-off-by: Vipin <vipin.kumar@st.com>

SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers

Signed-off-by: Vipin <vipin.kumar@st.com>

README.spear contains information about SPEAr architecture and
build options etc

Signed-off-by: Vipin <vipin.kumar@st.com>

Fetched from http://www.arm.linux.org.uk/developer/machines/download.php
And built with

repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm


commit 2045124ffd1a5e46d157349016a2c50f19c8c91d

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>

As per coding guidlines, it is good to maintain proper ordering
in the makefiles.
This was missed during initial coding, corrected here.

This was discovered during orion5x code review
Thanks to Albert Aribaud for this.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

These are few files directly imported from Linux kernel source.
Those are not modifyed at all ar per strategy.
These files contains source with GPLv2 only
whereas u-boot expects GPLv2 or latter

These files are updated for the same from prior permission from original writes

Acked-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.

l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control
for S3C6400. In the configuration of SMDK6400, however, two 16-bit
mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit
memory bus and there is no need to control CKE for each chip
separately. AFAIK, CKE1 is not at all connected. Only CKE0 is
used. Futhermore, it should be '0' always for S3C6410. When tested
with a board which has a S3C6410 and the same memory configuration,
a side effect is observed that u-boot command "reset" doesn't work
leading to system hang. Leaving the bit clear is safe in most cases.

Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch adds a CPLD
version detection for Kilauea and code to reconfigure the EBC controller
(chip select 2) for the old CPLD if no new version is found.

Additionally the CPLD version is printed upon bootup:

Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>

The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>

This is not only a cosmetic change as it fixes the real bug of board
reset not working with the ELDK 4.2 toolchain.

Signed-off-by: Detlev Zundel <dzu@denx.de>

It's useful to be able to build up the host tools without having to select
a board first.  Pretty much all tools in there are config-independent
anyways.

Also add a shortcut "tools-all" to quickly build all host tools that are
actually config-independent to allow for simple test builds.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

This code doesn't use any config.h defines, and the sha1.h header already
declares a sha1_csum prototype.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The u-boot command structures don't get used with host systems, so don't
bother including it when building host code.  This avoids an implicit need
on config.h in the process.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Matthias Weisser <weisserm@arcor.de>