In addition to the regular mux configuration, certain pins of DRA7
require to have "virtual mode" also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.

Provide easy to use macro to do the same.

For configuring virtual mode, along with normal pad configuration add
the following two steps:
- Select MODESELECT field of each assocaited PAD.
  CTRL_CORE_PAD_XXX[8]:MODESELECT = 1
- DELAYMODE filed should be configured with value given in DATA Manual.
  CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Update DDR IO register values.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Updating EMIF registers to enable HW leveling
on DRA7-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Updating EMIF registers to enable HW leveling
on BeagleBoard-X15.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

This commit imports some updates of kconfiglib.py from
https://github.com/ulfalizer/Kconfiglib



 - Warn about and ignore the "allnoconfig_y" Kconfig option
 - Statements in choices inherit menu/if deps
 - Add Symbol.is_allnoconfig_y()
 - Hint that modules are still supported despite warnings.
 - Add warning related to get_defconfig_filename().
 - Fix typo in docs.
 - Allow digits in $-references to symbols.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Signed-off-by: Philip Craig <philipjcraig@gmail.com>
Signed-off-by: Jakub Sitnicki <jsitnicki@gmail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Commit e11c6c27 broke calculating lr register
in function save_boot_params() and caused U-Boot to crash at early boot time
on Nokia N900 board.

This patch fix calculating return address in lr register and make Nokia N900
board bootable again. Patch was tested in qemu and also on real N900 HW.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>

sometimes it is usefull to know if board-detection has
written the correct value into gd->board_type.

For this we add some output to the bdinfo command.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>

Commit 9ba9e85f (net: Fix NET_RANDOM_ETHADDR dependencies)
accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards.

Prior to that commit, those boards defined CONFIG_LIB_RAND, but not
CONFIG_NET_RANDOM_ETHADDR.  So, commit 9ba9e85f should not have
touched them, but in fact it ripped CONFIG_LIB_RAND off from all the
header files, which caused undefined reference to srand and rand.
CONFIG_LIB_RAND=y must be revived for such boards.

BTW, this commit indeed makes it better, but even with this fix,
three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not
build due to region 'ram' overflowed error.  This was cause by
commit 6eed3786 (net: Move the CMD_NET config to defconfigs)
because CMD_NET selects NET, and NET selects REGEX.  Eventually,
some boards were newly enabled with CONFIG_REGEX, increasing the
memory footprint.  A patch is expected to fix the build error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Some AVR32 boards were dropped by the following commits:
 9eb45aab (avr32: delete non generic board favr-32-ezkit)
 e3693076 (avr32: delete non generic board hammerhead)
 c62d2f8f (avr32: delete non generic board mimc200)
 e5354b8a (avr32: delete non generic board's atstk100{3, 4, 6})

Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>

Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>

Allow SPL to be built with this option so that we can support device tree
control. Disable the simple bus for now in SPL. It may be needed later.

Signed-off-by: Simon Glass <sjg@chromium.org>

This is used when the full malloc() is not available.

Signed-off-by: Simon Glass <sjg@chromium.org>

This feature should be deprecated for new boards, and significantly adds
to SPL code size. Drop it. Instead, we can use stdout-path in the /chosen
node.

Signed-off-by: Simon Glass <sjg@chromium.org>

We plan to enable device tree in SPL by default. Before doing this,
explicitly disable it for all boards.

Signed-off-by: Simon Glass <sjg@chromium.org>

The 4KB padding doesn't seem necessary since we don't normally adjust the
control device tree file within U-Boot. Also drop the memory table space.

Signed-off-by: Simon Glass <sjg@chromium.org>

This option is used by some boards, so support it with driver model. This
is really ugly - we should rewrite this driver once all users are moved to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>

For 16-bit-per-pixel displays it is useful to support 8 bit-per-pixel
images to reduce image size. Add support for this when drawing BMP images.

Signed-off-by: Simon Glass <sjg@chromium.org>

We try to avoid typedefs and these ones are easy enough to remove. Before
changing this header in the next patch, remove the typedefs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Support this function so we can use Chrome OS verified boot with sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>

This function is used before jumping to U-Boot, but in that case we don't
always want to disable caches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>

For secure boot systems it is common to have a read-only U-Boot which starts
the machine and jumps to a read-write U-Boot for actual booting the OS. This
allows the read-write U-Boot to be upgraded without risk of permanently
bricking the machine. In the event that the read-write U-Boot is corrupted,
the read-only U-Boot can detect this with a checksum and boot into a
recovery flow.

To support this, add a way to detect when U-Boot is run from SPL as opposed
to some other method, such as booted directly (no SPL) or started from
another source (e.g. a primary U-Boot). This works by putting a special value
in r0.

For now we rely on board-specific code to actually check the register and
set a flag. At some point this could be generalised, perhaps by using a spare
register and passing a flag to _main and/or board_init_f().

This commit does not implement any feature, but merely provides the API for
boards to implement.

Signed-off-by: Simon Glass <sjg@chromium.org>

Support this function with driver model also (CONFIG_DM_USB).

Signed-off-by: Simon Glass <sjg@chromium.org>

Somehow this change was dropped in the various merges. I noticed when I
came to turn off the non-driver-model support for Tegra. We need to make
this change (and deal with any problems) before going further.

Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>

Add the legacy i2c_reg_read/write() functions to the compatibility layer
so that they can be used when CONFIG_DM_I2C_COMPAT is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>

Due to absence of CONFIG_SYS_64BIT_LBA, u-boot-sunxi currently has
no support for the (GPT) partioning scheme of large disks > 2TB.
While the AHCI driver seems to handle this nicely, the problem is
that lbaint_t values get truncated to 32-bit.

This patch sets CONFIG_SYS_64BIT_LBA from sunxi_common.h for all
SoCs that support AHCI (CONFIG_SUNXI_AHCI).

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

This fixes ethernet no longer working on boards which use a gpio to enable
the phy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

I have this board at work, so I can trun tests on it.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>