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  • Florian Mayer Florian Mayer fmayer
1 author
  1. Feb 21, 2015
  3. Dec 09, 2014
  5. Nov 23, 2014
  7. Aug 30, 2014
  9. Jul 28, 2014
  11. May 25, 2014
  13. Apr 17, 2014
  15. Feb 22, 2014
  17. Dec 01, 2013
  19. Oct 31, 2013
  21. Oct 03, 2013
    • Andre Przywara's avatar
      ARM: extend non-secure switch to also go into HYP mode · d4296887
      Andre Przywara authored 
      
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.

While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).

The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.

In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.

The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.

Signed-off-by: default avatarAndre Przywara <andre.przywara@linaro.org>
      d4296887
    • Andre Przywara's avatar
      ARM: add C function to switch to non-secure state · 1ef92385
      Andre Przywara authored 
      
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.

We check the availability of the security extensions first.

Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.

Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
   (GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
   (GICD_IGROUPRn = 0xFFFFFFFF)

The core specific GIC setup is then done in the assembly routine.

Signed-off-by: default avatarAndre Przywara <andre.przywara@linaro.org>
      1ef92385
    • Andre Przywara's avatar
      ARM: add secure monitor handler to switch to non-secure state · 45b940d6
      Andre Przywara authored 
      
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.

Signed-off-by: default avatarAndre Przywara <andre.przywara@linaro.org>
      45b940d6
  23. Aug 15, 2013
  25. Jul 24, 2013
  27. Mar 24, 2013
  29. Mar 07, 2013
  31. Jan 16, 2013
  33. Sep 01, 2012
  35. Mar 27, 2012
  37. Dec 06, 2011
  39. Aug 03, 2011
  41. Jul 04, 2011
    • Aneesh V's avatar
      armv7: cache maintenance operations for armv7 · 2c451f78
      Aneesh V authored 
      
- Add a framework for layered cache maintenance
	- separate out SOC specific outer cache maintenance from
	  maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
  caches known to ARMv7 CPUs. For instance in Cortex-A8 these
  opertions will affect both L1 and L2 caches. In Cortex-A9
  these will affect only L1 cache

- D-cache operations supported:
	- Invalidate entire D-cache
	- Invalidate D-cache range
	- Flush(clean & invalidate) entire D-cache
	- Flush D-cache range
- I-cache operations supported:
	- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
  used

Signed-off-by: default avatarAneesh V <aneesh@ti.com>
      2c451f78
  43. Nov 17, 2010
    • Sebastien Carlier's avatar
      Switch from archive libraries to partial linking · 6d8962e8
      Sebastien Carlier authored 
      
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils.  As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".

This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.

The name of each former library archive is preserved except for
extensions which change from ".a" to ".o".  This commit updates
references accordingly where needed, in particular in some linker
scripts.

This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols.  Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

Signed-off-by: default avatarSebastien Carlier <sebastien.carlier@gmail.com>
      6d8962e8
  45. Sep 29, 2010
  47. Jul 05, 2010
  49. Apr 13, 2010
  51. Jan 24, 2009
  53. Apr 13, 2008
  55. Apr 11, 2008
  57. Mar 30, 2008
  59. Oct 08, 2006