- Oct 22, 2012
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York Sun authored
Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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York Sun authored
These assembly macros simplify codes to add and delete temporary TLB entries. Signed-off-by:
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Kumar Gala authored
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York Sun authored
FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined. Remove the #ifdef. Signed-off-by:
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York Sun authored
Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT not defined. Signed-off-by:
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Shengzhou Liu authored
According to new QIXIS system definition, update QIXIS registers set to add present2 register instead of obsolete ctl_sys2. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by:
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Timur Tabi authored
Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by:Timur Tabi <timur@freescale.com> Signed-off-by:
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Laurentiu Tudor authored
Add a new device tree property named "fsl,liodn-offset-list" holding a list of per pci endpoint permitted liodn offsets. This property is useful in virtualization scenarios that implement per pci endpoint partitioning. The final liodn of a partitioned pci endpoint is calculated by the hardware, by adding these offsets to pci controller's base liodn, stored in the "fsl,liodn" property of its node. The liodn offsets are interleaved to get better cache utilization. As an example, given 3 pci controllers, the following liodns are generated for the pci endpoints: pci0: 193 256 259 262 265 268 271 274 277 pci1: 194 257 260 263 266 269 272 275 278 pci2: 195 258 261 264 267 270 273 276 279 Signed-off-by:Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by:
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Timur Tabi authored
The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by:
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Timur Tabi authored
The P5040 does not have SRIO support, so there are no SRIO LIODNs. Therefore, the functions that set the SRIO LIODNs should not be compiled. Signed-off-by:
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Laurentiu Tudor authored
The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by:
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Timur Tabi authored
Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by:
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Liu Gang authored
Erratum: A-004034 Affects: SRIO Description: During port initialization, the SRIO port performs lane synchronization (detecting valid symbols on a lane) and lane alignment (coordinating multiple lanes to receive valid data across lanes). Internal errors in lane synchronization and lane alignment may cause failure to achieve link initialization at the configured port width. An SRIO port configured as a 4x port may see one of these scenarios: 1. One or more lanes fails to achieve lane synchronization. Depending on which lanes fail, this may result in downtraining from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane). 2. The link may fail to achieve lane alignment as a 4x, even though all 4 lanes achieve lane synchronization, and downtrain to a 1x. An SRIO port configured as a 1x port may fail to complete port initialization (PnESCSR[PU] never deasserts) because of scenario 1. Impact: SRIO port may downtrain to 1x, or may fail to complete link initialization. Once a port completes link initialization successfully, it will operate normally. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
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ramneek mehresh authored
Fix usb device-tree fixup: - wrong modification of dr_mode and phy_type when "usb1" is not mentioned inside hwconfig string; now allows hwconfig strings like: "usb2:dr_mode=host,phy_type=ulpi" - add warning message for using usb_dr_mode and usb_phy_type env variables (if either is used) Signed-off-by:
Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by:
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Zang Roy-R61911 authored
P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the workaround conditional. In formal release document, the errata number should be ESDHC13 instead of ESDHC136. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
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Prabhakar Kushwaha authored
QIXIS FPGA layout defines the address of registers but The actual register bit implementation is board-specific, So avoid use of magic numbers as it may vary across different boards's QIXIS FPGA implementation. Also, Avoid board specific defines in common/qixis.h Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
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Mark Marshall authored
We should only write TSR_WIS to the SPRN_TSR register in reset_85xx_watchdog. The old code would cause the timer interrupt to be acknowledged when the watchdog was reset, and we would then get no more timer interrupts. This bug would affect all mpc85xx boards that have the watchdog enabled. Signed-off-by:
Mark Marshall <Mark.Marshall@omicron.at> Signed-off-by:
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Chris Packham authored
Users of familiar with the Linux gpiolib API expect that value parameter to gpio_direction_output reflects the initial state of the output pin. gpio_direction_output was always driving the output low, now it drives it high or low according to the value provided. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Minghuan Lian authored
The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by:
Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by:
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- Oct 20, 2012
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git://git.denx.de/u-boot-armTom Rini authored
Conflicts: drivers/serial/serial_lh7a40x.c Signed-off-by:Tom Rini <trini@ti.com>
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- Oct 19, 2012
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Albert ARIBAUD authored
Colored logs confuse patman when analyzing logs. Add --no-color option in git log commands in case the default config has color. Signed-off-by:
Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
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Simon Glass authored
This doesn't need to be a long, so change it. Signed-off-by:
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Simon Glass authored
This doesn't need to be a long, so change it. Signed-off-by:
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Simon Glass authored
This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by:
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Simon Glass authored
This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by:
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Simon Glass authored
This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by:
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Simon Glass authored
This does not need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by:
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Simon Glass authored
These don't need to be longs, so change them. Signed-off-by:
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Hung-Te Lin authored
To support Non-ASCII keys (ex, Fn, PgUp/Dn, arrow keys, ...), we need to translate key code into escape sequence. (Updated by sjg@chromium.org to move away from a function to store keycodes, so we can easily record how many were sent. We now need to return this from input_send_keycodes() so we know whether keys were generated.) Signed-off-by:
Hung-Te Lin <hungte@chromium.org> Signed-off-by:
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Marc Jones authored
The i8042 keyboard reset was not checking the results of the output buffer after the reset command. This can jam up some KBC/keyboards. Also, remove a write to the wrong register and the CONFIG setting around the incorrect write. Signed-off-by:
Marc Jones <marc.jones@chromium.org> Signed-off-by:
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Louis Yung-Chieh Lo authored
The BIOS leaves the keyboard enabled during boot time so that any keystroke would interfere kernel driver initialization. Add a way to disable the keyboard to make sure no scancode will be generated during the boot time. Note that the keyboard will be re-enabled again after the kernel driver is up. This code can be called from the board functions. Signed-off-by:
Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by:
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Gabe Black authored
This change adds a board overridable function which can be used to decide whether or not to initialize the i8042 keyboard controller. On systems where it isn't actually connected to anything, this can save a significant amount of boot time. On Stumpy, this saves about 200ms on boot. Signed-off-by:
Gabe Black <gabeblack@chromium.org> Signed-off-by:
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Gabe Black authored
On x86, the i8042 keyboard controller driver frequently waits for the keyboard input buffer to be empty to make sure the controller has had a chance to process the data it was given. The way the delay loop was structured, if the controller hadn't cleared the corresponding status bit immediately, it would wait 1ms before checking again. If the keyboard responded quickly but not instantly, the driver would still wait a full 1ms when perhaps 1us would have been sufficient. Because udelay is a busy wait anyway, this change decreases the delay between checks to 1us. Also, this change gets rid of a hardcoded 250ms delay. On Stumpy, this saves 100-150ms during boot. Signed-off-by:
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