Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add code to set up the Local Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This is no-longer used, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Actually initr_enable_interrupts() was never called in an x86 build
due to it was wrapped by CONFIG_x86 (typo of X86).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

Since cpu_init_interrupts() was moved out of cpu_init_r(), it is
useless to keep cpu_init_r() for x86, thus remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

Currently cpu_init_interrupts() is called from cpu_init_r() to
setup the interrupt and exception of the cpu core, but at that
time the i8259 has not been initialized to mask all the irqs
and remap the master i8259 interrupt vector base, so the whole
system is at risk of being interrupted, and if interrupted,
wrong interrupt/exception message is shown.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add init for XHCI so that high-speed USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>

Enable USB support on link - there are two EHCI ports available.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add init for EHCI so that USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add the requires settings to enable SATA on link.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add some settings required to set up the LPC correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>

These peripherals should not be at the top level, since they exist inside
the PCI bus. We don't have a full device tree node for pci yet, but we
should at least put it at the right level.

Signed-off-by: Simon Glass <sjg@chromium.org>

Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>

Add required init for the Intel Platform Controller Hub in ivybridge.

Signed-off-by: Simon Glass <sjg@chromium.org>

We don't use many features yet, so this only has a few declarations.
It will be expanded as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add basic setup for the PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>

Add this additional init in case it is needed by the OS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Some PCI functions cannot be auto-configured. Add a function to set up a
fixed BAR which can be used in these situations. Also add a function to read
the current address of a BAR.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Enable this option so that we can configure the available PCI devices. Also
make sure that PCI is available early after relocation as we use it for
several other subsystems.

Signed-off-by: Simon Glass <sjg@chromium.org>

Some boards will want to do some setup before and after a PCI hose
is scanned.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Add definitions for the I/O Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>

Provide a function to set up the RTC ready for use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Define the reset base in config.mk so that it does not need to be calculated
twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values
to fit with this new approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This normally indicates a problem which will prevent relocation from
functioning, resulting in a hang. Panic in this case to make it easier
to debug.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

This was taken from Linux 3.18 with some additional IDs from Chrome OS
Coreboot commit 688ef385.

Signed-off-by: Simon Glass <sjg@chromium.org>

Device trees must be aligned to a 4-byte boundary. This was dropped in the
Kbuild conversion. Bring it back, and use 16-byte alignment for good
measure.

Signed-off-by: Simon Glass <sjg@chromium.org>

This new symbol may be defined by the compiler. If it is, avoid a compiler
warning when USE_STDINT is defined.

Signed-off-by: Simon Glass <sjg@chromium.org>

It is now required to add subdirectories in the x86 cpu Makefile. Add this
to fix a build breakage for chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Tom Rini <trini@ti.com>

128059b9 ("hush: fix segfault on syntax error") attempted to fix a
segfault on syntax errors, but it broke Ctrl-C handling, and the
assumption that it made, that rcode could not be -1, is incorrect.
Revert this change.

Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Reported-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Rabin Vincent <rabin@rab.in>

Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <trini@ti.com>

Conflicts:
	arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>

Fabio Estevam authored 10 years ago and Stefano Babic committed 10 years ago

When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Cc: Eric Benard <eric@eukrea.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>