- Jul 07, 2012
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Shiraz Hashim authored
Enable data cache with 1:1 mapping of DDR to enable fast file transfer over tty which was doing lot of copy. This feature is enabled only for flashing operation i.e. when CONFIG_SPEAR_USBTTY is enabled. This has been tested on SPEAr320, SPEAr600 and SPEAr900 evaluation boards. Following figures show an estimate on the performance improvements. The test setup was a Linux host (not Windows) and involved measurement of only binary transfer time, through kermit. The flash erase and flash copy time would be unaffected by these patches. Another thing is this that the timings remained more or less same across ARM9 and Cortex based devices, hence reporting only one of the cases. Before Enhancements =================== $ time ukermit.small -p /dev/ttyACM0 -f spear320_uImage.img Downloading file: 100.00% completed(2014080/2014080 bytes) real 0m41.228s user 0m0.002s sys 0m0.064s After Enhancements ================== $ time ukermit.large -p /dev/ttyACM0 -f spear320_uImage.img Downloading file: 100.00% completed(2014080/2014080 bytes) real 0m5.441s user 0m0.001s sys 0m0.001s Signed-off-by:
Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by:
Amit Virdi <amit.virdi@st.com> Signed-off-by:
Stefan Roese <sr@denx.de>
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Shiraz Hashim authored
Enabling autoneg avoids situation on few phys with fixed configuration. For example, in one situation, nfs boot timed out when phy configuration is 100Mbps. In another situtation, when traffic is directed to SPEAr, either thru cross-cable or thru switch, the TFTP or DHCP command in u-boot starts to timeout very often. When Autoneg is ON, same phys started working perfectly. Reported-by:
Deepak Sikri <deepak.sikri@st.com> Reported-by:
Armando Visconti <armando.visconti@st.com> Signed-off-by:
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Vipin KUMAR authored
This patch enables the UDC and usb-console support only for usbtty configurations Signed-off-by:
Vipin Kumar <vipin.kumar@st.com> Signed-off-by:
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Vipin KUMAR authored
This patch enables the support for usb high speed device for spear platform SOCs Signed-off-by:
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Amit Virdi authored
flash reading is required earlier than flash_init is called since the env_init is called before flash_init. This makes the smi_init necessary before env_init being called. Signed-off-by:
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Vipin KUMAR authored
This patch modifies the default environment variables as: 1. Default bootargs: - console=ttyAMA0,115200 - For environment present in NOR flash root=/dev/mtdblock3 - For environment present in NAND flash root=/dev/mtdblock7 - Removes "mem=" option 2. Introduces CONFIG_EXTRA_ENV_USBTTY as default usbtty env var even when usbtty is not selected 3. Add default definitions for nfsboot and ramboot 4. Add a new default environment variable(CONFIG_EXTRA_ENV_UNLOCK) for SPEAr310 and SPEAr320 Signifacance of CONFIG_EXTRA_ENV_USBTTY: This environment variable is important for flashing utility to work. So if somebody accidently erases the env sector then also this variable must be preserved so that flashing utility functions properly. Signifacance of CONFIG_EXTRA_ENV_UNLOCK: This env variable is read by the cfi driver to unlock all flash sectors. This is necessary because the Parallel NOR flash connected on the spear310 and spear320 boards, M28W64, has all its sectors in locked state at reset and these have to be unlocked explicitly before being erased or written. Signed-off-by: -
Vipin KUMAR authored
SPEAr doesn't need CONFIG_SYS_HZ_CLOCK. This commit removes it. Signed-off-by:
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Vipin KUMAR authored
This patch adds options for all the below mentioned configurations and subsequently renames the include/configs/spearxxx.h files to spear3xx_evb.h, spear6xx_evb.h etc to depict evaluation board configuration. SPEAr3xx and SPEAr6xx boards can be compiled in following configurations 1. Environment placed in NAND 2. Console on usb device 3. Console on usb device with environment placed in NAND 4. SPEAr310 and SPEAr320 support environment variables in parallel NOR flash. Signed-off-by:
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Vipin KUMAR authored
Earlier, architecture specific init code was mixed with board initialization code in board/spear/... This patch updates architecture support for SPEAr in latest u-boot and prints the SoC information. Signed-off-by:
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Vipin Kumar authored
Few Designware peripheral registers need to be modified based on the ethernet interface selected by the board. This patch supports interface information in ethernet driver Signed-off-by:
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Vipin KUMAR authored
SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The driver for this device is already supported by u-boot, so configuring board configuration file and defining base addresses etc to make use of the common driver Signed-off-by:
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Vipin KUMAR authored
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Vipin KUMAR authored
ethaddr can be optionally read from i2c memory. So, chip_config command supports reading/writing hw mac id into i2c memory. Placing this code within CONFIG_CMD_NET as this would only be needed when network interface is configured Signed-off-by:
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Amit Virdi authored
Xloader table was used primarily to inform u-boot about the DDR size. However, now the ddr size is calculated at runtime which eliminates any need for the Xloader table. So removing this unnecessary code. Signed-off-by:
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Amit Virdi authored
While the u-boot code is running from the flash, it is essential that no access is made to the bss segment. This is due to the fact that .rel.dyn and .bss areas overlap and former contains information used in relocation. In SPEAr, this was not taken into consideration. As a result, while the relocation wasn't complete, dram_init populated an uninitialized global variable resulting in corruption of .rel.dyn area, which resulted in u-boot crash. This commit fixes this problem by removing code that accesses bss segment Signed-off-by:
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Armando Visconti authored
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Amit Virdi authored
There are two problems in the current timeout loop implementation: 1. In case initial test failing, there will always be a delay of 1 ms 2. The delay duration is not tunable The new implementation addresses both these limitations. Signed-off-by:
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Armando Visconti authored
If the flash size was smaller than 1MB then flash_print_info() was erroneously reporting 0 MB. Signed-off-by:
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Armando Visconti authored
THis patch introduces a new methodology for flash probing in which flash_devices[] table, looked-up thru the dev_id, is used to locate the flash geometry and information. Signed-off-by:
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Armando Visconti authored
Since the smi erase code is very generic and works for any kind of flash, there is no need to test for ST_M25Pxx_ID flash types like m25p40 flashes). Signed-off-by:
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Vipin Kumar authored
smi_read_sr fails sometimes because of TFF not getting set within assumed time. This condition may arise because of, for example, smi memory being in a erase mode. This fix is to enable reading the status register until timeout. Signed-off-by:
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Shiraz Hashim authored
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Vipin KUMAR authored
SMI driver read status fails because the control register could not be overwritten. Instead, the read status should be tried until timeout. Signed-off-by:
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Amit Virdi authored
This commit does the following: - Reports error if SNOR flash is not found on the board - Changes smi_read_sr to return error using which a retry mechanism is implemented for reading flash status Signed-off-by:
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Amit Virdi authored
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Amit Virdi authored
Curently the code makes wrong assumption that the Transfer finished flag shall be set within the stipulated time. However, there may occur a scenario in which the TFF flag is not set. Return error in that case. Signed-off-by:
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Vipin KUMAR authored
SMI is the serial memory interface controller provided by ST. Earlier, a driver exists in the u-boot source code for the SMI IP. However, it was specific to spear platforms. This commit converts the same driver to a more generic driver. As a result, the driver files are renamed to st_smi.c and st_smi.h and moved into drivers/mtd folder for reusability by other platforms using smi controller peripheral. Signed-off-by:
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Vipin KUMAR authored
Since, SPEAr platform uses generic FSMC driver now, so spear specific files drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Vipin KUMAR authored
Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device Signed-off-by:
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Vipin KUMAR authored
Flexible static memory controller is a peripheral provided by ST, which controls the access to NAND chips along with many other memory device chips eg NOR, SRAM. This patch adds the driver support for FSMC controller interfacing with NAND memory. Signed-off-by:
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Holger Brunck authored
These functions tried to access two static tables before relocation (board_early_init_f is executed before relocation). But these static tables lie in the bss section which is not valid before relocation. These accesses then overwrote some parts of u-boot binary before it was relocated. For the kmnusa build, this results in a corrupted important env variable (bootcmd) but it may be that some other parts of the u-boot binary are corrupted. This patch solves this problem by moving all the kw_gpio_* calls to board_init, which should be early enough in the boot sequence. The only calls that could not be moved is the one for the SOFT (bitbang) I2C, and they have been replaced by a direct access to the GPIO dataout Control register to set the two GPIOs as output. Signed-off-by:Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
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Thomas Herzmann authored
Add a function to read the dip_switch on kmcoge5un. If the switch is set the actual_bank is set to 0 and this SW is booted. Signed-off-by:
Thomas Herzmann <thomas.herzmann@keymile.com> Signed-off-by:
Holger Brunck <holger.brunck@keymile.com>
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Valentin Longchamp authored
The PCIe FPGAs now have to support 2 resets: one for the non traffic affecting part (PCIe) and one for the traffic affecting part. When the FPGA is not reconfigured, we only reset the PCIe part. Signed-off-by: -
Valentin Longchamp authored
In order to be able to perform board resets without interrupting the traffic, the configuration of an already properly configured FPGA is skipped. This is because some PCIe FPGAs embed some other function that must continue to work over reset. It is then the responsibility of the application to trigger a reconfiguration when needed. This is done by lowering the FPGA_INIT_B pin for delaying the configuration to u-boot @ next reboot, and then lower the FPGA_PROGRAM_B signal. Signed-off-by: -
Valentin Longchamp authored
Some very similar #defines for reg addresses are used in a later patch (managed_switch support for km_arm). Signed-off-by: -
Holger Brunck authored
Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place. Signed-off-by:
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Valentin Longchamp authored
This adds a first support of the FPGA download for a PCIe FPGA based on the BOCO2 CPLD. This takes place in 3 steps, all done accessing the SPICTRL reg of the BOCO2: 1) start the FPGA config with an access to the FPGA_PROG bit 2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1 for the end of the FPGA configuration (with a timeout) 3) reset the FPGA 4) finally remove the access to its config EEPROM from the FPGA so that the CPU can update the FPGA configuration when the kernel is running The boards with a PCIe FPGA but without BOCO2 still are supported. The config option name is CONFIG_KM_FPGA_CONFIG Signed-off-by:
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Holger Brunck authored
The additional headerfile is unneeded here, we can use the generic km_kirkwood.h instead. And we can use the better config option KM_PIGGY4_88E6061 for the specific features for boards with this design in km_arm.c. Signed-off-by:
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Holger Brunck authored
Use the generic header km_kirkwood.h and get rid of the board specific header. changes for v2: rebased because of changes in other patches Signed-off-by:
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Holger Brunck authored
For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver. Signed-off-by:
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